Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective - researchr publication authors

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Payam Heydari, Massoud Pedram. Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective. In 19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings. pages 209-213, IEEE Computer Society, 2001.

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