Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective

Payam Heydari, Massoud Pedram. Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective. In 19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings. pages 209-213, IEEE Computer Society, 2001.

@inproceedings{HeydariP01a,
  title = {Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective},
  author = {Payam Heydari and Massoud Pedram},
  year = {2001},
  tags = {design},
  researchr = {https://researchr.org/publication/HeydariP01a},
  cites = {0},
  citedby = {0},
  pages = {209-213},
  booktitle = {19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-1200-3},
}