Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura. A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, South Korea, October 25-28, 2016. pages 297-300, IEEE, 2016. [doi]
@inproceedings{HidaIAM16,
title = {A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors},
author = {Itaru Hida and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2016},
doi = {10.1109/APCCAS.2016.7803958},
url = {http://dx.doi.org/10.1109/APCCAS.2016.7803958},
researchr = {https://researchr.org/publication/HidaIAM16},
cites = {0},
citedby = {0},
pages = {297-300},
booktitle = {2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, South Korea, October 25-28, 2016},
publisher = {IEEE},
isbn = {978-1-5090-1570-2},
}