Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation - researchr publication authors

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Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu. Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. In 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India. pages 781-786, IEEE Computer Society, 2007. [doi]

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