Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu. Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. In 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India. pages 781-786, IEEE Computer Society, 2007. [doi]
@inproceedings{HigamiSTT07,
title = {Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation},
author = {Yoshinobu Higami and Kewal K. Saluja and Hiroshi Takahashi and Yuzo Takamatsu},
year = {2007},
doi = {10.1109/VLSID.2007.83},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.83},
tags = {test coverage, testing, coverage},
researchr = {https://researchr.org/publication/HigamiSTT07},
cites = {0},
citedby = {0},
pages = {781-786},
booktitle = {20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India},
publisher = {IEEE Computer Society},
isbn = {0-7695-2502-4},
}