Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita. Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. In 8th Asian Test Symposium (ATS 99), 16-18 November 1999, Shanghai, China. pages 141-146, IEEE Computer Society, 1999. [doi]
Abstract is missing.