Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization

Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera. Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization. In 31st IEEE International System-on-Chip Conference, SOCC 2018, Arlington, VA, USA, September 4-7, 2018. pages 112-117, IEEE, 2018. [doi]

Abstract

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