Abstract is missing.
- A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System DesignsChien-Tung Liu, Zhe-Wei Chang, Shih-Nung Wei, Jinn-Shyan Wang, Tay-Jyi Lin. 1-6 [doi]
- An Ultra-Low-Voltage Sub-Threshold Pseudo-Differential CMOS Schmitt TriggerYasin Bastan, Ali Nejati, Sara Radfar, Parviz Amiri, Mehdi Nasrollahpour, Sotoudeh Hamedi-Hagh. 1-5 [doi]
- Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in Parallel ComputingHemanta Kumar Mondal, Rodrigo Cadore Cataldo, César Augusto Missio Marcon, Kevin Martin, Sujay Deb, Jean-Philippe Diguet. 1-6 [doi]
- 0.5V 1OMS/S 9-Bits Asynchronous SAR ADC for BLE Receivers in L80NM CMOS TechnologyHugo Hernandez, Lucas C. Severo, Wilhelmus A. M. Van Noije. 1-4 [doi]
- On a New Hardware Trojan Attack on Power Budgeting of Many Core SystemsYiming Zhao, Xiaohang Wang, Yingtao Jiang, Mei Yang, Amit Kumar Singh, Terrence S. T. Mak. 1-6 [doi]
- Holistic Energy Management with μProcessor Co-Optimization in Fully Integrated Battery-Less IoTsJosiah D. Hester, Tianyu Jia, Jie Gu. 7-12 [doi]
- Cloud Motion Vector Estimation Using Scalable Wireless Sensor NetworksMichael Adelbert Gacusan, V. Muthukumar. 13-18 [doi]
- A Discontinuous Charging Technique with Programmable Duty-Cycle for Switched-Capacitor Based Energy Harvesting Circuits in IoT ApplicationsSanad Kawar, Shoba Krishnan, Khaldoon Abugharbieh. 19-22 [doi]
- An FSK Transceiver for USB Power Delivery in 0.14-μm CMOS TechnologySiamak Delshadpour, Ahmad Yazdi, Michael Geng, Xu Zhang, Abhijeet Kulkarni, Ken Jaramillo. 23-28 [doi]
- A 64 dB Dynamic Range Programmable Gain Amplifier for Dual Band WLAN 802.11abg IF Receiver in 0.18 μm CMOS TechnologySiamak Delshadpour. 29-32 [doi]
- Design and Analysis of 66GHz Voltage Controlled Oscillators for FMCW Radar Applications with Phase Noise Impact ConsiderationMehdi Nasrollahpour, Amir Mahdavi, Sotoudeh Hamedi-Hagh. 33-36 [doi]
- A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic SystemsMd Musabbir Adnan, Sagarvarma Sayyaparaju, Garrett S. Rose, Catherine D. Schuman, Bon Woong Ku, Sung Kyu Lim. 37-42 [doi]
- A Low-Power Arithmetic Element for Multi-Base Logarithmic Computation on Deep Neural NetworksJiawei Xu, Yuxiang Huan, Li-Rong Zheng, Zhuo Zou. 43-48 [doi]
- Taxonomy of Spatial Parallelism on FPGAs for Massively Parallel ApplicationsArnab A. Purkayastha, Suhas Ashok Shiddhibhavi, Hamed Tabkhi. 55-60 [doi]
- A New Circuit Topology for High-Performance Pulsed Time-of- Flight Laser Radar ReceiversKaiyou Li, Haoxin Zheng, Bing Mo, Jianping Guo, Dihu Chen. 78-83 [doi]
- Policy-Based Security Modelling and Enforcement Approach for Emerging Embedded ArchitecturesMatthew Hagan, Fahad Siddiqui, Sakir Sezer. 84-89 [doi]
- An Entropy Analysis Based Intrusion Detection System for Controller Area Network in VehiclesQian Wang, Zhaojun Lu, Gang Qu. 90-95 [doi]
- A High-Performance VLSI Architecture of the Present Cipher and its Implementations for SoCsJai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Abhijit Karmakar, Raj Singh. 96-101 [doi]
- Leakage Power Analysis (LPA) Attack in Breakdown Mode and CountermeasureWeize Yu, Yiming Wen. 102-105 [doi]
- Optimized Counter-Based Multi-Ported Memory Architectures for Next-Generation FPGAsS. Navid Shahrouzi, Darshika G. Perera. 106-111 [doi]
- Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-OptimizationTatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera. 112-117 [doi]
- An ASIC Design of Multi-Electrode Digital Basket Catheter Systems with Reconfigurable Compressed SamplingHaoming Chu, Yuxiang Huan, Dongxuan Bao, Bengt Källbäck, Yajie Qin, Zhuo Zou, Lirong Zheng. 124-129 [doi]
- A Multi-Objective Architecture Optimization Method for Application-Specific Noc DesignChangqing Xu, Yi Liu, Yintang Yang. 130-135 [doi]
- Building an Acceleration Overlay for Novice StudentsShrikant S. Jadhav, Noah LaMoyne, Alan Chen 0003, Clay Gloster, Dylan Yang, Sunmin Yun, Youngsoo Kim. 136-139 [doi]
- Pro-Active Policing and Policy Enforcement Architecture for Securing MPSoCsFahad Siddiqui, Matthew Hagan, Sakir Sezer. 140-145 [doi]
- Compact Modeling and Design of Magneto-Electric Transistor Devices and CircuitsN. Sharma, C. Binek, A. Marshall, J. P. Bird, P. A. Dowben, D. Nikonov. 146-151 [doi]
- Flexible Self-Healing Router for Reliable and High-Performance Network-an-Chips ArchitectureKasem Khalil, Omar Eldash, Ashok Kumar 0001, Magdy Bayoumi. 152-157 [doi]
- Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level SynthesisMattia Cacciotti, Vincent Camus, Jeremy Schlachter, Alessandro Pezzotta, Christian Enz. 158-162 [doi]
- PAT-Noxim: A Precise Power & Thermal Cycle-Accurate NoC SimulatorAmin Norollah, Danesh Derafshi, Hakem Beitollahi, Ahmad Patooghy. 163-168 [doi]
- PCNNA: A Photonic Convolutional Neural Network AcceleratorArmin Mehrabian, Yousra Al-Kabani, Volker J. Sorger, Tarek A. El-Ghazawi. 169-173 [doi]
- Data Readout Triggering for Phase 2 of the Belle II Particle Detector Experiment Based on Neural NetworksSteffen Baehr, Fabian Kempf, Jürgen Becker. 174-179 [doi]
- Towards Designing Optimized Low Power Reversible Demultiplexer for Emerging NanocircuitsLafifa Jamal, Md. Riaz Uddint. 180-185 [doi]
- Noise Aware Power Adaptive Partitioned Deep Networks for Mobile Visual Assist PlatformsPeter A. Zientara, Jack Sampson, Vijaykrishnan Narayanan. 186-191 [doi]
- An Automated Fault Injection Platform for Fault Tolerant FFT Implemented in SRAM-Based FPGAChuang-An Mao, Yu Xie, Yizhuang Xie, He Chen, Hao Shi. 192-196 [doi]
- A Quantitative Approach to SoC Functional Safety AnalysisShivakumar Chonnad, Radu Iacob, Vladimir Litovtchenko. 197-202 [doi]
- A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP TechnologyAnkush Mamgain, Anuj Grover. 203-208 [doi]
- Reconfigurable Clock Generator with Wide Frequency Range and Single-Cycle Phase and Frequency SwitchingKeyvan Ramezanpour, Paul Ampadu. 206-212 [doi]
- An Output-Capacitorless Adaptively Biased Low-Dropout Regulator with Maximum 132-MHz UGF and Without Minimum Loading RequirementSiji Huang, Yicheng Li, Bing Mo, Jianping Guo, Dihu Chen. 206-212 [doi]
- A Scalable High-Precision and High-Throughput Architecture for Emulation of Quantum AlgorithmsNaveed Mahmud, Esam El-Araby. 206-212 [doi]
- Universal CMOS Diamond-Graph Circuit for Embedded ComputingShun-Wen Cheng, Chun-Pin Lin, Chi-Shi Chen, Wei-Chang Tsai. 206-212 [doi]
- A Content - Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing TechniqueTanja Harbaum, Matthias Balzer, Marc Weber, Jürgen Becker. 206-212 [doi]
- A Practical Sense Amplifier Design for Memristive Crossbar Circuits (PUF)Mesbah Uddin, Garrett S. Rose. 209-214 [doi]
- Reducing Memory Interference Latency of Safety-Critical Applications via Memory Request Throttling and Linux CgroupJungho Kim, Philkyue Shin, Soonhyun Noh, Daesik Ham, Seongsoo Hong. 215-220 [doi]
- Memory Access Driven Memory Layout and Block Replacement Techniques for Compressed Deep Neural NetworksByungmin Ahn, Taewhan Kim. 221-226 [doi]
- A Learning-Guided Hierarchical Approach for Biomedical Image SegmentationHuaipan Jiang, Anup Sarma, Jihyun Ryoo, Jagadish B. Kotra, Meena Arunachalam, Chita R. Das, Mahmut T. Kandemir. 227-232 [doi]
- Designing Algorithm for the High Speed TIQ ADC, with Improved AccuracyJun Hyuk Park, Soobum Kwon, Kyusun Choi. 233-237 [doi]
- MPT: Multiple Parallel Tempering for High-Throughput MCMC SamplersMorteza Hosseini, Rashidul Islam, Lahir Marni, Tinoosh Mohsenin. 244-249 [doi]
- Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT ApplicationsPei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen, Chien-Tung Liu, Tay-Jyi Lin, Jinn-Shyan Wang. 250-253 [doi]
- Co-Optimizing CPUs and Accelerators in Constrained SystemsAlec Roelke, Mircea R. Stan. 254-259 [doi]
- Power- Thermal Aware Balanced Task-Resource Co-Allocation in Heterogeneous Many CPU-GPU Cores NoC in Dark Silicon EraMd Farhadur Reza, Dan Zhao, Magdy Bayoumi. 260-265 [doi]
- A Methodology for Low-Power Approximate Embedded SRAM Within Multimedia ApplicationsSamira Ataei, James E. Stine. 266-271 [doi]
- 0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS ProcessYun-Sheng Chan, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang. 272-277 [doi]
- Energy-Efficient SRAM Design with Data-Aware Dual-Modes L0T Storage Cell for CNN ProcessorsHan Xu, Fei Qiao, Zhe Chen, Qi Wei 0001, Xinjun Liu, Huazhong Yang. 278-283 [doi]
- A One-to-Many Traffic Aware Wireless Network-in-Package for Multi-Chip Computing PlatformsM. Meraj Ahmed, Amlan Ganguly, Sajeed Mohaamd Shahriat, Hardeep Pruswani, Naseef Mansoor. 284-289 [doi]
- Centralized Priority Management Allocation for Network-on-Chip RouterPengzhan Yan, Ramalingam Sridhar. 290-295 [doi]
- A 32kHz Crystal Oscillator Leveraging Voltage Scaling in an Ultra-Low Power 40NA Real-Time ClockMathieu Coustans, François Krummenacher, Maher Kayal, Lucas Rossi, Mario Dellea, Yves Godat, Yves Sierro, Silvio DallaPiazza. 308-313 [doi]
- Integrated Surround & CMS Automotive SoCMihir Mody, Kedar Chitnis, Piyali Goswami, Brijesh Jada, Shiju Sivasankaran, Gregory Shurtz, Rajat Sagar, Abhinay Armstrong, Shashank Dabral, Prasad Jondhale, Yashwant Dutt, Jason Jones. 318-321 [doi]
- 10T Differential-Signal SRAM Design in a L4-NM FinFET Technology for High-Speed ApplicationMotoi Ichihashi, Youngtag Wood, Muhammed Ahosan Ul Karim, Vivek Joshi, David Burnett. 322-325 [doi]
- Low Power 20.625 Gbps Type-C USB3.2/DPl.4/ Thunderbolt3 Combo Linear Redriver in 0.25 μm BiCMOS TechnologySiamak Delshadpour, Ahmad Yazdi, Soon-Gil Jung, Xu Zhang, Michael Geng, Leo Liu, Ranjeet Kumar Gupta. 326-329 [doi]