Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume. Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design. In 27th IEEE Asian Test Symposium, ATS 2018, Hefei, China, October 15-18, 2018. pages 7-12, IEEE, 2018. [doi]
Abstract is missing.