Abstract is missing.
- Identification of Faulty TSV with a Built-In Self-Test MechanismDilip Kumar Maity, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman. 1-6 [doi]
- Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan DesignSatoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume. 7-12 [doi]
- A Fault Check Graph Approach for Photonic Router in Network on ChipAijun Zhu, Duanyong Chen, Chuan-pei Xu, Cong Hu, Aiguo Song. 13-18 [doi]
- A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM CircuitMeng-Chi Chen, Tsung-Hsuan Wu, Cheng-Wen Wu. 19-24 [doi]
- Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor MemoryPeng Liu, Jigang Wu, Zhiqiang You, Michael Elimu, Weizheng Wang, Shuo Cai. 25-29 [doi]
- On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BISTShigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara. 30-35 [doi]
- Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx FeaturesAmitava Majumdar, Balakrishna Jayadev. 36-41 [doi]
- A Dictionary-Based Test Data Compression Method Using Tri-State CodingTian Chen, Chenxin Lin, Huaguo Liang, Fuji Ren. 42-47 [doi]
- A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot AttacksChia-Chi Wu, Man-Hsuan Kuo, Kuen-Jong Lee. 48-53 [doi]
- A Low-Cost High-Efficiency True Random Number Generator on FPGAsGaoliang Ma, Huaguo Liang, Liang Yao, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Kai Zhou. 54-58 [doi]
- An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAsXiumin Xu, Huaguo Liang, Kai Zhou, Gaoliang Ma, Zhengfeng Huang, Maoxiang Yi, Tianming Ni, Yingchun Lu. 59-62 [doi]
- A High Reliability FPGA Chip Identification Generator Based on PDLsKai Zhou, Huaguo Liang, Yue Jiang, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yao Yao. 63-67 [doi]
- Hardware Trojan in FPGA CNN AcceleratorJing Ye, Yu Hu, Xiaowei Li 0001. 68-73 [doi]
- Lifetime Reliability Trojan Based on Exploring Malicious AgingTien-Hung Tseng, Shou-Chun Li, Kai-Chiang Wu. 74-79 [doi]
- Hardware Trojan Detection Based on Signal CorrelationWei Zhao, Haihua Shen, Huawei Li, Xiaowei Li. 80-85 [doi]
- Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOSAibin Yan, Yafei Ling, Kang Yang, Zhili Chen, Maoxiang Yi. 86-91 [doi]
- Extending Aging Monitors for Early Life and Wear-Out Failure PreventionChang Liu 0010, Eric Schneider, Matthias Kampmann, Sybille Hellebrand, Hans-Joachim Wunderlich. 92-97 [doi]
- Cell Flipping with Distributed Refresh for Cache Ageing MinimizationShengyu Duan, Basel Halak, Mark Zwolinski. 98-103 [doi]
- A New Scheme to Extract PUF Information by Scan ChainAijiao Cui, Wei Zhou, Gang Qu, Huawei Li. 104-108 [doi]
- CIPA: Concurrent IC and PCB Authentication Using On-chip Ring Oscillator ArrayYueying Han, Xiaoxiao Wang, Mark Tehranipoor. 109-114 [doi]
- PUF Based Pay-Per-Device Scheme for IP Protection of CNN ModelQingli Guo, Jing Ye, Yue Gong, Yu Hu, Xiaowei Li. 115-120 [doi]
- A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICEZhengfeng Huang, Yangyang Zhang, Zian Su, Huaguo Liang, Huijie Yao, Tianming Ni. 121-126 [doi]
- Towards Affordable Fault-Tolerant Nanosatellite Computing with Commodity HardwareChristian M. Fuchs, Nadia M. Murillo, Aske Plaat, Erik van der Kouwe, Peng Wang. 127-132 [doi]
- RiskCap: Minimizing Effort of Error Regulation for Approximate ComputingShuhao Jiang, Jiajun Li, Xin He, Guihai Yan, Xuan Zhang, Xiaowei Li. 133-138 [doi]
- Dynamic Fine-Grain Power Gating Design in WiNoCYiming Ouyang, Lizhu Hu, Yifeng Wu, Jianfeng Yang, Kun Xing. 139-148 [doi]
- Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan TestingYucong Zhang, Xiaoqin Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Hans-Joachim Wunderlich, Jun Qian. 149-154 [doi]
- Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BISTSenling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima. 155-160 [doi]
- Progressive ECC Techniques for Phase Change MemoryShyue-Kung Lu, Hui-Ping Li, Kohei Miyase. 161-166 [doi]
- Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM StorageMamoru Ishizaka, Michihiro Shintani, Michiko Inoue. 167-172 [doi]
- Precompensation, BIST and Analogue Berger Codes for Self-Healing of Neuromorphic RRAMTsung-Chu Huang, Jeffae Schroff. 173-178 [doi]
- Digital Rights Management for Paper-Based Microfluidic BiochipsJian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho. 179-184 [doi]
- Test Diagnosis of Digital Microfluidic Biochips Using Image SegmentationSourav Ghosh, Hafizur Rahaman, Chandan Giri. 185-190 [doi]
- A Monobit Built-In Test and Diagnostic System for Flexible Electronic InterconnectJun-Yang Lei, Thomas Moon, Justin Chow, Suresh K. Sitaraman, Abhijit Chatterjee. 191-196 [doi]
- Highly Efficient Waveform Acquisition Condition in Equivalent-Time Sampling SystemYuto Sasaki, Yujie Zhao, Anna Kuwana, Haruo Kobayashi. 197-202 [doi]
- Time-to-Digital Converter Architectures Using Two Oscillators with Different FrequenciesKosuke Machida, Uni Ozawa, Yudai Abe, Haruo Kobayashi. 203-208 [doi]
- Design and Implementation of an FPGA-Based 16-Channel Data/Timing FormatterGuan-Hao Hou, Wei-Chen Huang, Jiun-Lang Huang, Terry Kuo. 209-214 [doi]