Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda. A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks. IJNC, 10(2):84-93, 2020. [doi]
@article{HirayamaAMT20,
title = {A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks},
author = {Yuki Hirayama and Tetsuya Asai and Masato Motomura and Shinya Takamaeda},
year = {2020},
url = {http://www.ijnc.org/index.php/ijnc/article/view/222},
researchr = {https://researchr.org/publication/HirayamaAMT20},
cites = {0},
citedby = {0},
journal = {IJNC},
volume = {10},
number = {2},
pages = {84-93},
}