Weng-Geng Ho, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang. High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016. pages 1762-1765, IEEE, 2016. [doi]
@inproceedings{HoLNCGC16,
title = {High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits},
author = {Weng-Geng Ho and Nan Liu and Kyaw Zwa Lwin Ne and Kwen-Siong Chong and Bah-Hwee Gwee and Joseph Sylvester Chang},
year = {2016},
doi = {10.1109/ISCAS.2016.7538909},
url = {http://dx.doi.org/10.1109/ISCAS.2016.7538909},
researchr = {https://researchr.org/publication/HoLNCGC16},
cites = {0},
citedby = {0},
pages = {1762-1765},
booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016},
publisher = {IEEE},
isbn = {978-1-4799-5341-7},
}