A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman. A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. J. Solid-State Circuits, 35(5):713-718, 2000. [doi]

Authors

Heinz Hoenigschmid

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Alexander Frey

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John K. DeBrosse

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Toshiaki Kirihata

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Gerhard Mueller

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Daniel W. Storaska

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Gabriel Daniel

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Gerd Frankowsky

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Kevin P. Guay

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David R. Hanson

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Louis Lu-Chen Hsu

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Brian Ji

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Dmitry G. Netis

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Steve Panaroni

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Carl Radens

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Armin M. Reith

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Hartmud Terletzki

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Oliver Weinfurtner

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Johann Alsmeier

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Werner Weber

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Matthew R. Wordeman

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