The following publications are possibly variants of this publication:
- A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processorAtsushi Mohri, Akira Yamada 0005, Y. Yoshida, Hisakazu Sato, Hidehiro Takata, K. Nakakimura, M. Hashizume, Y. Shimotsuma, K. Tsuchihashi. jssc, 34(7):992-1000, 1999. [doi]
- A new RISC processor architecture for MPEG-2 decodingKunihiro Yamada, Masanori Kojima, Toru Shimizu, Fumiaki Sato, Tadanori Mizuno. tce, 48(1):143-150, 2002. [doi]