Reduction of minimum operating voltage (V::DDmin::) of CMOS logic circuits with post-fabrication automatically selective charge injection - researchr publication authors

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Kentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai. Reduction of minimum operating voltage (V::DDmin::) of CMOS logic circuits with post-fabrication automatically selective charge injection. In Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim, editors, Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010. pages 175-180, ACM, 2011. [doi]

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