Zheng-Hao Hong, Wei-Zen Chen. A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, KaoHsiung, Taiwan, November 10-12, 2014. pages 277-280, IEEE, 2014. [doi]
@inproceedings{HongC14-6,
title = {A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery},
author = {Zheng-Hao Hong and Wei-Zen Chen},
year = {2014},
doi = {10.1109/ASSCC.2014.7008914},
url = {http://dx.doi.org/10.1109/ASSCC.2014.7008914},
researchr = {https://researchr.org/publication/HongC14-6},
cites = {0},
citedby = {0},
pages = {277-280},
booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, KaoHsiung, Taiwan, November 10-12, 2014},
publisher = {IEEE},
isbn = {978-1-4799-4090-5},
}