Table of Contents

• Mobile display technologies: Past, present and futureHiroyuki Ohshima. 1-4 [doi]
• Internet of Things: Evolution towards a hyper-connected societyAlex Jinsung Choi. 5-8 [doi]
• A reconfigurable analog baseband for single-chip, Saw-less, 2G/3G/4G cellular transceivers with carrier aggregationJongwoo Lee, Byungki Han, Jae Hyun Lim, Su-Seob Ahn, Jae Kwon Kim, Thomas Cho. 9-12 [doi]
• A low-power single-chip transceiver for 169/300/400/900 MHz band wireless sensor networksMakoto Oba, Eiji Okada, Ayako Tachibana, Koji Takahashi, Masahiko Sagisaka. 13-16 [doi]
• A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communicationJun Deguchi, T. Yamagishi, Hideaki Majima, N. Ozaki, K. Hiwada, Makoto Morimoto, T. Ashitani, Shouhei Kousai. 17-20 [doi]
• A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capabilityHiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto. 21-24 [doi]
• 40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issuesYoshisato Yokoyama, Yuichiro Ishii, Koji Tanaka, Tatsuya Fukuda, Yoshiki Tsujihashi, Atsushi Miyanishi, Shinobu Asayama, Keiichi Maekawa, Kazutoshi Shiba, Koji Nii. 25-28 [doi]
• A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughputKenta Yasufuku, Naoto Oshiyama, Toshitada Saito, Yukimasa Miyamoto, Yutaka Nakamura, Ryota Terauchi, Atsushi Kondo, Takuma Aoyama, Masafumi Takahashi, Yukihito Oowaki, Ryoichi Bandai. 29-32 [doi]
• A 0.43pJ/bit true random number generatorTing-Kuei Kuan, Yu-Hsuan Chiang, Shen-Iuan Liu. 33-36 [doi]
• A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array acceleratorItaru Hida, Dahoo Kim, Tetsuya Asai, Masato Motomura. 37-40 [doi]
• A sub-threshold to super-threshold Level Conversion Flip Flop for sub/near-threshold dual-supply operationChao Wang, Jun Zhou, Xin Liu, Muthukumaraswamy Annamalai Arasu, Minkyu Je. 41-44 [doi]
• Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoringIslam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera. 45-48 [doi]
• Ultra-low voltage datapath blocks in 28nm UTBB FD-SOIHans Reyserhove, Nele Reynders, Wim Dehaene. 49-52 [doi]
• A body bias generator with wide supply-range down to threshold voltage for within-die variability compensationNorihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Hidetoshi Onodera. 53-56 [doi]
• A monolithic capacitor-current-controlled hysteretic buck converter with transient-optimized feedback circuitShih-Hsiung Chien, Ting-Hsuan Hung, Szu-Yu Huang, Tai-Haur Kuo. 57-60 [doi]
• th-Order ControlDong-Chul Park, Tae-Hwang Kong, Sukhwan Choi, Gyu-Hyeong Cho. 61-64 [doi]
• CCM/GM relative skip energy control in single-inductor multiple-output DC-DC converter for wearable device power solutionYi-Ping Su, Chiun-He Lin, Te-Fu Yang, Ru-Yu Huang, Wei-Chung Chen, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chao-Cheng Lee. 65-68 [doi]
• A current-mode buck converter with bandwidth reconfigurable for enhanced efficiency and improved load transient responsePai-Yi Wang, Li-Te Wu, Tai-Haur Kuo. 69-72 [doi]
• A 20MS/s buck/boost supply modulator for envelope tracking applications with direct digital interfaceShang-Hsien Yang, Chin-Long Wey, Ke-Horng Chen, Ying-Hsi Lin, Jing-Jia Chen, Tsung-Yen Tsai, Chao-Cheng Lee. 73-76 [doi]
• A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOSChun-Cheng Liu. 77-80 [doi]
• A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOSYao-Sheng Hu, Chi-Huai Shih, Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen. 81-84 [doi]
• A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifierJames Lin, Zule Xu, Masaya Miyahara, Akira Matsuzawa. 85-88 [doi]
• 2 in 32 nm SOI CMOSLukas Kull, Jan Pliva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici. 89-92 [doi]
• A 12 bit 250 MS/s 28 mW +70 dB SFDR DAC in 0.11 μm CMOS using controllable RZ window for wireless SoC integrationSeonggeon Kim, Jaehyun Kang, MinJae Lee. 93-96 [doi]
• A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOSShih Hao Huang, Zheng-Hao Hong, Wei-Zen Chen. 97-100 [doi]
• A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS processSang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Jiho Joo, Gyungock Kim, Deog Kyoon Jeong. 101-104 [doi]
• A 23mW/lane 1.2-6.8Gb/s multi-standard transceiver in 28nm CMOSSeong Ho Lee, Duke Tran, Tamer A. Ali, Burak Çatli, Heng Zhang, Wei Zhang, Mohammed M. Abdul-Latif, Zhi Huang, Guansheng Li, Mahmoud Reza Ahmadi, Afshin Momtaz. 105-108 [doi]
• Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technologyGuan-Sing Chen, Chin-Yang Wu, Chen-Lun Lin, Hao-Wei Hung, Jri Lee. 109-112 [doi]
• A power management unit integrated ADSL/ADSL2+ CPE analog front-end with -93.5dB THD for DMT-based applicationsYu-Kai Chou, Yue Feng, Yu-Hsin Lin, Cong Liu, Chen-Yen Ho, Bo Hu, Jun Zha, Steven Chuang. 113-116 [doi]
• Semiconductor innovation into the next decadeJack Y.-C. Sun. 117-120 [doi]
• Energy efficient computing in nanoscale CMOS: Challenges and opportunitiesVivek De. 121-124 [doi]
• A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channelHyunbae Lee, Taeksang Song, Sangyeon Byeon, Kwanghun Lee, Inhwa Jung, Seongjin Kang, Ohkyu Kwon, Koeun Cheon, Donghwan Seol, Jong-Ho Kang, GunWoo Park, Yunsaing Kim. 125-128 [doi]
• 0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOSPo-Tsang Huang, Shu-Lin Lai, Ching-Te Chuang, Wei Hwang, Jason Huang, Angelo Hu, Paul Kan, Michael Jia, Kimi Lv, Bright Zhang. 129-132 [doi]
• A nonvolatile look-up table using ReRAM for reconfigurable logicWen-Pin Lin, Shyh-Shyuan Sheu, Chia-Chen Kuo, Pei-Ling Tseng, Meng-Fan Chang, Keng-Li Su, Chih-Sheng Lin, Kan-Hsueh Tsai, Sih-Han Lee, Szu-Chieh Liu, Yu-Sheng Chen, Heng-Yuan Lee, Ching-Chih Hsu, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao. 133-136 [doi]
• A 6-bit drift-resilient readout scheme for multi-level Phase-Change MemoryAravinthan Athmanathan, Milos Stanisavljevic, Junho Cheon, Seokjoon Kang, Changyong Ahn, Junghyuk Yoon, Min Chul Shin, Taekseung Kim, Nikolaos Papandreou, Haris Pozidis, Evangelos Eleftheriou. 137-140 [doi]
• 0.2 V 8T SRAM with improved bitline sensing using column-based data randomizationAnh-Tuan Do, Zhao Chuan Lee, Bo Wang, Ik Joon Chang, Tony Tae-Hyoung Kim. 141-144 [doi]
• A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOSChing-Wei Wu, Ming-Hung Chang, Chia-Cheng Chen, Robin Lee, Hung-Jen Liao, Jonathan Chang. 145-148 [doi]
• A CMOS thermistor-embedded continuous-time delta-sigma temperature sensor with a resolution of 0.01 °CChan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin. 149-152 [doi]
• An area-efficient capacitively-coupled instrumentation amplifier with a duty-cycled Gm-C DC servo loop in 0.18-μm CMOSChih-Chan Tu, Feng-Wen Lee, Tsung-Hsien Lin. 153-156 [doi]
• Highly improved SNR differential sensing method using parallel operation signaling for touch screen applicationSanghyun Heo, Hyunggun Ma, Jae-Joon Kim, Franklin Bien. 157-160 [doi]
• A 16.6μW 32.8MHz monolithic CMOS relaxation oscillatorYat-Hei Lam, Seong-Jin Kim. 161-164 [doi]
• An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64% in 16nm FinFETChin-Ho Chang, Jaw-Juinn Horng, Amit Kundu, Chih-Chiang Chang, Yung-Chow Peng. 165-168 [doi]
• CMOS THz transmissive imaging systemTzu-Chao Yan, Chun-Hsing Li, Chih-Wei Lai, Wei-Cheng Chen, Tzu-Yuan Chao, Chien-Nan Kuo. 169-172 [doi]
• 23Gbps 9.4pJ/bit 80/100GHz band CMOS transceiver with on-board antenna for short-range communicationKensuke Nakajima, Akihiro Maruyama, Masato Kohtani, Tsuyoshi Sugiura, Eiichiro Otobe, Jaejin Lee, Shinhee Cho, Kyusub Kwak, Jeongseok Lee, Toshihiko Yoshimasu, Minoru Fujishima. 173-176 [doi]
• A 3 Gb/s 64-QAM E-band direct-conversion transmitter in 40-nm CMOSDixian Zhao, Patrick Reynaert. 177-180 [doi]
• 2 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAsRui Wu, Qinghong Bu, Wei Deng, Kenichi Okada, Akira Matsuzawa. 181-184 [doi]
• 54 GHz CMOS LNAs with 3.6 dB NF and 28.2 dB gain using transformer feedback Gm-boosting techniqueShita Guo, Tianzuo Xi, Ping Gui, Jing Zhang, Wooyeol Choi, K. O. Kenneth, Yanli Fan, Daquan Huang, Richard Gu, Mark Morgan. 185-188 [doi]
• A 0.5-V sub-μW/channel neural recording IC with delta-modulation-based spike detectionSeong-Jin Kim, Lei Liu, Lei Yao, Wang Ling Goh, Yuan Gao, Minkyu Je. 189-192 [doi]
• A 10.4 mW electrical impedance tomography SoC for portable real-time lung ventilation monitoring systemSunjoo Hong, Jaehyuk Lee, Joonsung Bae, Hoi-Jun Yoo. 193-196 [doi]
• A power efficient frequency shaping neural recorder with automatic bandwidth adjustmentJian Xu, Tong Wu, Zhi Yang. 197-200 [doi]
• A 20V-compliance implantable neural stimulator IC with closed-loop power control, active charge balancing, and electrode impedance checkLei Yao, Jianming Zhao, Peng Li, Rui-Feng Xue, Yong Ping Xu, Minkyu Je. 201-204 [doi]
• A 330μW, 64-channel neural recording sensor with embedded spike feature extraction and auto-calibrationAlberto Rodriguez-Perez, Manuel Delgado-Restituto, Angela A. Darie, Cristina Soto-Sánchez, Eduardo Fernandez-Jover, Ángel Rodríguez-Vázquez. 205-208 [doi]
• A 27mW reconfigurable marker-less logarithmic camera pose estimation engine for mobile augmented reality processorInjoon Hong, Gyeonghoon Kim, Youchang Kim, Donghyun Kim, Byeong-Gyu Nam, Hoi-Jun Yoo. 209-212 [doi]
• A 4.9 mW neural network task scheduler for congestion-minimized network-on-chip in multi-core systemsYouchang Kim, Gyeonghoon Kim, Injoon Hong, Donghyun Kim, Hoi-Jun Yoo. 213-216 [doi]
• An 87×49 mutual capacitance touch sensing IC enabling 0.5 mm-diameter stylus signal detection at 240 Hz-reporting-rate with palm rejectionShin-ichi Yoshida, Mutsumi Hamaguchi, Takahiro Morishita, Shinji Shinjo, Akira Nagao, Masayuki Miyamoto. 217-220 [doi]
• A 2.5W tablet speaker delivering 3.2W pseudo high power by psychoacoustic model based adaptive power management systemShin-Hao Chen, Shen-Yu Peng, Ke-Horng Chen, Shin-Chi Lai, Sheng Kang, Kevin Cheng, Ying-Hsi Lin, Chen-Chih Huang, Chao-Cheng Lee. 221-224 [doi]
• An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processorNoriyuki Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, Makoto Nagata. 225-228 [doi]
• A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area networkChih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee. 229-232 [doi]
• A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvementJen-Huan Tsai, Sheng-An Ko, Hui-Huan Wang, Chia-Wei Wang, Hsin Chen, Po-Chiun Huang. 233-236 [doi]
• A 12-V charge pump-based square wave driver in 65-nm CMOS technologyYousr Ismail, Chih-Kong Ken Yang. 237-240 [doi]
• A programmable discrete-time filter employing hardware-efficient two-dimensional implementation methodJaeyoung Choi, M. Kumarasamy Raja, M. Annamalai Arasu. 241-244 [doi]
• A low-input-swing AC-DC voltage multiplier using Schottky diodesYe-Sing Luo, Shen-Iuan Liu. 245-248 [doi]
• A 0.1-5GHz flexible SDR receiver in 65nm CMOSXinwang Zhang, Yang Xu, Bingqiao Liu, Qian Yu, Siyang Han, Qiongbing Liu, Zehong Zhang, Yanqiang Gao, Zhihua Wang, Baoyong Chi. 249-252 [doi]
• 2 4-channel UWB beamforming receiver with Q-compensation in 65nm CMOSLei Wang, Yong Lian, Chun-Huat Heng. 253-256 [doi]
• A fully-integrated reconfigurable dual-band transceiver for short range wireless communication in 180nm CMOSXiaobao Yu, Meng Wei, Yun Yin, Ying Song, Siyang Han, Qiongbing Liu, Zongming Jin, Xiliang Liu, Zhihua Wang, Baoyong Chi. 257-260 [doi]
• A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applicationsYang Li, Ni Xu, Yining Zhang, Woogeun Rhee, Sanghoon Kang, Zhihua Wang. 261-264 [doi]
• An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSIHiroyuki Ito, Yoshihiro Yoneda, Taiki Ibe, Taisuke Hamada, Noboru Ishihara, Kazuya Masu, Shoichi Masui, Youichi Momiyama. 265-268 [doi]
• A 103 pJ/bit multi-channel reconfigurable GMSK/PSK/16-QAM transmitter with band-shapingXiayun Liu, Teng Kok Hin, Chun-Huat Heng, Yuan Gao, Wei-Da Toh, San-Jeow Cheng, Minkyu Je. 269-272 [doi]
• A 5-20 Gb/s power scalable adaptive linear equalizer using edge countingYuan-Fu Lin, Chang-Cheng Huang, Jiunn-Yih Max Lee, Chih-Tien Chang, Shen-Iuan Liu. 273-276 [doi]
• A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recoveryZheng-Hao Hong, Wei-Zen Chen. 277-280 [doi]
• A 2×25 Gb/s clock and data recovery with background amplitude-locked loopChien-Kai Kao, Kuan-Lin Fu, Shen-Iuan Liu. 281-284 [doi]
• 2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOIAravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa. 285-288 [doi]
• A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuitLi-Hung Chiueh, Tai-Cheng Lee. 289-292 [doi]
• A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoringKelvin Yi-Tse Lai, Yu-Tao Yang, Bang-Jing Chen, Chun-Jen Shen, Ming-Feng Shiu, Zih-Cheng He, Hsie-Chia Chang, Chen-Yi Lee. 293-296 [doi]
• A 5.2mW IEEE 802.15.6 HBC standard compatible transceiver with power efficient delay-locked-loop based BPSK demodulatorHyunwoo Cho, Hyungwoo Lee, Joonsung Bae, Hoi-Jun Yoo. 297-300 [doi]
• A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensorWenfeng Zhao, Rui Pan, Yajun Ha, Zhi Yang. 301-304 [doi]
• A 135-μW 0.46-mΩ/√Hz thoracic impedance variance monitor with square-wave current modulationChih-Chan Tu, Feng-Wen Lee, Dong-Feng Yeih, Tsung-Hsien Lin. 305-308 [doi]
• A 10μA on-chip electrochemical impedance spectroscopy system for wearables/implantablesJingren Gu, Huanfen Yao, Keping Wang, Babak A. Parviz, Brian P. Otis. 309-312 [doi]
• 22.5 dB open-loop gain, 31 kHz GBW pseudo-CMOS based operational amplifier with a-IGZO TFTs on a flexible filmKoichi Ishida, Reza Shabanpour, Bahman Kheradmand Boroujeni, Tilo Meister, Corrado Carta, Frank Ellinger, Luisa Petti, Niko Munzenrieder, Giovanni A. Salvatore, Gerhard Tröster. 313-316 [doi]
• 2 98.5dB SNDR hybrid audio delta-sigma modulator with digital ELD compensation in 28nm CMOSTze-Chien Wang, Yu-Hsin Lin, Chun-Cheng Liu. 317-320 [doi]
• A 1 V 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedbackYi Zhang, Chia-Hung Chen, Tao He, Xin Meng, Nancy Qian, Ed Liu, Phillip Elliott, Gabor C. Temes. 321-324 [doi]
• A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOSCheng-En Hsieh, Shen-Iuan Liu. 325-328 [doi]
• A 10b 100kS/s SAR ADC with charge recycling switching methodKai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin. 329-332 [doi]
• RF transconductor linearization technique robust to process, voltage and temperature variationsHarish Kundur Subramaniyan, Eric A. M. Klumperink, Bram Nauta, Venkatesh Srinivasan, Ali Kiaei. 333-336 [doi]
• A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixerChin-Fu Li, Shih-chieh Chou, Chang-Ming Lai, Cuei-Ling Hsieh, Jenny Yi-Chun Liu, Po-Chiun Huang. 337-340 [doi]
• An ultra-low-cost ESD-protected 0.65dB NF +10dBm OP1dB GNSS LNA in 0.18-μm SOI CMOSFei Song, Sam Chun-Geik Tan, Osama Shana'a. 341-344 [doi]
• A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposersNai-Chung Kuo, Bonjern Yang, Chaoying Wu, Lingkai Kong, Angie Wang, Michael Reiha, Elad Alon, Ali M. Niknejad, Borivoje Nikolic. 345-348 [doi]
• A 44.9% PAE digitally-assisted linear power amplifier in 40 nm CMOSHaoyu Qian, José Silva-Martínez. 349-352 [doi]
• A 0.1-1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibrationXinwang Zhang, Zhihua Wang, Baoyong Chi. 353-356 [doi]
• A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technologySang-Gyun Kim, Seung-Hwan Jung, Yun-Seong Eo, Seung-Hoon Kim, Xiao Ying, Hanbyul Choi, Chaerin Hong, Kyungmin Lee, Sung Min Park. 357-360 [doi]
• 2 all-digital delay-locked loop in 65-nm CMOSChun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, Chi-Tien Sun, Yuan-Hua Chu, Tzu-Yi Yang. 361-364 [doi]
• A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFETSho Ikeda, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu. 365-368 [doi]
• A novel 2.4-to-3.6 GHz wideband subharmonically injection-locked PLL with adaptively-aligned injection timingZhao Zhang, Liyuan Liu, Nanjian Wu. 369-372 [doi]
• Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processorYifan YangGong, Sebastian Turullols, Daniel Woo, Changku Huang, King C. Yen, Venkatram Krishnaswamy, Kalon Holdbrook, Jinuk Luke Shin. 373-376 [doi]
• A DC-46Gb/s 2: 1 multiplexer and source-series terminated driver in 20nm CMOS technologyJian Hong Jiang, Samir Parikh, Mark Lionbarger, Nikola Nedovic, Takuji Yamamoto. 377-380 [doi]
• What is a good way to expand a silicon value to a solution value?Tzi-Dar Chiueh, Toru Shimizu, Gregory Chen, Chen-Yi Lee, Charles Hsu, Tihao Chiang, Zhihua Wang, Junghwan Choi, Jongwoo Lee, Yasumoto Tomita, Takayuki Kawahara. 389-394 [doi]