Hyunbae Lee - researchr alias

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Viewing Publication 1 - 8 from 8

2020

A 12-b 2 MS/s R-C Two-Step SAR ADC with Bit-Cycling Time Control and LSB Correction LogicHyeokjoon Yang, Hyunbae Lee, Hanseul Kim, Sangwook Park, Jinwook Burm. isocc 2020: 238-239 [doi]

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detectorChangzhi Yu, Himchan Park, Qiwei Huang, Daewung Lee, Hyunmook Kim, Hyunbae Lee, Jinwook Burm. ieiceee, 17(6):20200024, 2020. [doi]

2016

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMsJi-Hoon Lim, Jun-Hyun Bae, Jaemin Jang, Hae Kang Jung, Hyunbae Lee, Yongju Kim, Byungsub Kim, Jae-Yoon Sim, Hong June Park. tcas, 63-II(2):141-145, 2016. [doi]

2015

A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier ChannelHyunbae Lee, Taeksang Song, Sangyeon Byeon, Kwanghun Lee, Inhwa Jung, Seongjin Kang, Ohkyu Kwon, Koeun Cheon, Donghwan Seol, Jong-Ho Kang, GunWoo Park, Yunsaing Kim. jssc, 50(11):2613-2624, 2015. [doi]

2014

2013

A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RXSoo-Min Lee, Jong-Hoon Kim, Jong-Sam Kim, Yunsaing Kim, Hyunbae Lee, Jae-Yoon Sim, Hong June Park. isscc 2013: 308-309 [doi]

2004

Level 1 & Victim Cache Management with Processor Reuse InformationJong Wook Kwak, Hyunbae Lee, Cheol Hong Kim, Sung-Hoon Shim, Chu Shik Jhon. pdpta 2004: 694-698

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