Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao. A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard. IEICE Electronic Express, 10(9):20130210, 2013. [doi]
@article{HongHZM13,
title = {A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard},
author = {Liang Hong and Weifeng He and Hui Zhu and Zhigang Mao},
year = {2013},
doi = {10.1587/elex.10.20130210},
url = {http://dx.doi.org/10.1587/elex.10.20130210},
researchr = {https://researchr.org/publication/HongHZM13},
cites = {0},
citedby = {0},
journal = {IEICE Electronic Express},
volume = {10},
number = {9},
pages = {20130210},
}