A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery

Zheng-Hao Hong, Yao-Chia Liu, Wei-Zen Chen. A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery. J. Solid-State Circuits, 50(11):2625-2634, 2015. [doi]

Abstract

Abstract is missing.