Steven F. Hoover. Timing-Abstract Circuit Design in Transaction-Level Verilog. In 2017 IEEE International Conference on Computer Design, ICCD 2017, Boston, MA, USA, November 5-8, 2017. pages 525-532, IEEE Computer Society, 2017. [doi]
@inproceedings{Hoover17,
title = {Timing-Abstract Circuit Design in Transaction-Level Verilog},
author = {Steven F. Hoover},
year = {2017},
doi = {10.1109/ICCD.2017.91},
url = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2017.91},
researchr = {https://researchr.org/publication/Hoover17},
cites = {0},
citedby = {0},
pages = {525-532},
booktitle = {2017 IEEE International Conference on Computer Design, ICCD 2017, Boston, MA, USA, November 5-8, 2017},
publisher = {IEEE Computer Society},
isbn = {978-1-5386-2254-4},
}