Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation - researchr publication

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Bernhard Hoppe, Gerd Neuendorf, Doris Schmitt-Landsiedel, J. Will Specks. Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation. IEEE Trans. on CAD of Integrated Circuits and Systems, 9(3):236-247, 1990. [doi]

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