A Selective Trigger Scan Architecture for VLSI Testing

Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi. A Selective Trigger Scan Architecture for VLSI Testing. IEEE Transactions on Computers, 57(3):316-328, 2008. [doi]

@article{HosseinabadySLN08,
  title = {A Selective Trigger Scan Architecture for VLSI Testing},
  author = {Mohammad Hosseinabady and Shervin Sharifi and Fabrizio Lombardi and Zainalabedin Navabi},
  year = {2008},
  doi = {10.1109/TC.2007.70806},
  url = {http://doi.ieeecomputersociety.org/10.1109/TC.2007.70806},
  tags = {architecture, testing},
  researchr = {https://researchr.org/publication/HosseinabadySLN08},
  cites = {0},
  citedby = {0},
  journal = {IEEE Transactions on Computers},
  volume = {57},
  number = {3},
  pages = {316-328},
}