A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistors

Mats Høvin, Dag T. Wisland, Yngvar Berg, Tor Sverre Lande. A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistors. In ISCAS (4). pages 397-400, 2002. [doi]

Authors

Mats Høvin

This author has not been identified. Look up 'Mats Høvin' in Google

Dag T. Wisland

This author has not been identified. Look up 'Dag T. Wisland' in Google

Yngvar Berg

This author has not been identified. Look up 'Yngvar Berg' in Google

Tor Sverre Lande

This author has not been identified. Look up 'Tor Sverre Lande' in Google