Mats Høvin, Dag T. Wisland, Yngvar Berg, Tor Sverre Lande. A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistors. In ISCAS (4). pages 397-400, 2002. [doi]
@inproceedings{HovinWBL02,
title = {A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistors},
author = {Mats Høvin and Dag T. Wisland and Yngvar Berg and Tor Sverre Lande},
year = {2002},
doi = {10.1109/ISCAS.2002.1010724},
url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2002.1010724},
researchr = {https://researchr.org/publication/HovinWBL02},
cites = {0},
citedby = {0},
pages = {397-400},
booktitle = {ISCAS (4)},
}