Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers - researchr publication authors

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Hsiang-Chih Hsiao, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh, Pei-Yin Chen. Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers. In 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2019, Cluj-Napoca, Romania, April 24-26, 2019. pages 1-4, IEEE, 2019. [doi]

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