Hsiang-Chih Hsiao, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh, Pei-Yin Chen. Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers. In 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2019, Cluj-Napoca, Romania, April 24-26, 2019. pages 1-4, IEEE, 2019. [doi]
@inproceedings{HsiaoCWSC19,
title = {Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers},
author = {Hsiang-Chih Hsiao and Chun-Wei Chen and Jonas Wang and Ming-Der Shieh and Pei-Yin Chen},
year = {2019},
doi = {10.1109/DDECS.2019.8724671},
url = {https://doi.org/10.1109/DDECS.2019.8724671},
researchr = {https://researchr.org/publication/HsiaoCWSC19},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2019, Cluj-Napoca, Romania, April 24-26, 2019},
publisher = {IEEE},
isbn = {978-1-7281-0073-9},
}