Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA - researchr publication authors

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Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang. Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. In Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008. pages 10-15, IEEE, 2008. [doi]

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