An all-digital phase-locked loop (ADPLL)-based clock recovery circuit

Terng-Yin Hsu, Bai-Jue Shieh, Chen-Yi Lee. An all-digital phase-locked loop (ADPLL)-based clock recovery circuit. J. Solid-State Circuits, 34(8):1063-1073, 1999. [doi]

Abstract

Abstract is missing.