An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication

Xianwu Hu, Yu Wang, Zizhao Ma, Gan Wen, Zeming Wang, Zhichao Lu, Yunlong Liu, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie. An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication. IEEE Trans. Circuits Syst. II Express Briefs, 70(11):4216-4220, November 2023. [doi]

Authors

Xianwu Hu

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Yu Wang

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Zizhao Ma

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Gan Wen

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Zeming Wang

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Zhichao Lu

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Yunlong Liu

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Yanlei Li

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Xingdong Liang

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Xiaoyang Zeng

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Yufeng Xie

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