Xianwu Hu, Yu Wang, Zizhao Ma, Gan Wen, Zeming Wang, Zhichao Lu, Yunlong Liu, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie. An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication. IEEE Trans. Circuits Syst. II Express Briefs, 70(11):4216-4220, November 2023. [doi]
@article{HuWMWWLLLLZX23,
title = {An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication},
author = {Xianwu Hu and Yu Wang and Zizhao Ma and Gan Wen and Zeming Wang and Zhichao Lu and Yunlong Liu and Yanlei Li and Xingdong Liang and Xiaoyang Zeng and Yufeng Xie},
year = {2023},
month = {November},
doi = {10.1109/TCSII.2023.3283418},
url = {https://doi.org/10.1109/TCSII.2023.3283418},
researchr = {https://researchr.org/publication/HuWMWWLLLLZX23},
cites = {0},
citedby = {0},
journal = {IEEE Trans. Circuits Syst. II Express Briefs},
volume = {70},
number = {11},
pages = {4216-4220},
}