Automated Synthesis of Safe Timing Behaviors for Requirements Models Using CCSL

Ming Hu 0003, Jun Xia, Min Zhang 0002, Xiaohong Chen 0007, Frédéric Mallet, Mingsong Chen. Automated Synthesis of Safe Timing Behaviors for Requirements Models Using CCSL. IEEE Trans. on CAD of Integrated Circuits and Systems, 42(12):5127-5140, December 2023. [doi]

Abstract

Abstract is missing.