An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires - researchr publication authors

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Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang, Sumeet Kumar Gupta. An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. In 2018 International Conference on IC Design & Technology, ICICDT 2018, Otranto, Italy, June 4-6, 2018. pages 117-120, IEEE, 2018. [doi]

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