Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang, Sumeet Kumar Gupta. An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. In 2018 International Conference on IC Design & Technology, ICICDT 2018, Otranto, Italy, June 4-6, 2018. pages 117-120, IEEE, 2018. [doi]
@inproceedings{HuangCWG18,
title = {An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires},
author = {Ya-Chi Huang and Meng-Hsueh Chiang and Shui-Jinn Wang and Sumeet Kumar Gupta},
year = {2018},
doi = {10.1109/ICICDT.2018.8399770},
url = {https://doi.org/10.1109/ICICDT.2018.8399770},
researchr = {https://researchr.org/publication/HuangCWG18},
cites = {0},
citedby = {0},
pages = {117-120},
booktitle = {2018 International Conference on IC Design & Technology, ICICDT 2018, Otranto, Italy, June 4-6, 2018},
publisher = {IEEE},
isbn = {978-1-5386-2550-7},
}