Jiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng 0001. A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization. In ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 18-21, 2021. pages 146-151, ACM, 2021. [doi]
Abstract is missing.