Table of Contents

• A DSM-based Polar Transmitter with 23.8% System EfficiencyYuncheng Zhang, Bangan Liu, Xiaofan Gu, Chun Wang, Atsushi Shirane, Kenichi Okada. 1-2 [doi]
• A 0.41W 34Gb/s 300GHz CMOS Wireless TransceiverIbrahim Abdo, Takuya Fujimura, Tsuyoshi Miura, Korkut Kaan Tokgoz, Atsushi Shirane, Kenichi Okada. 3-4 [doi]
• Capacitive Sensor Circuit with Relative Slope-Boost Method Based on a Relaxation OscillatorRyo Onishi, Koki Miyamoto, Korkut Kaan Tokgoz, Noboru Ishihara, Hiroyuki Ito. 5-6 [doi]
• 28GHz Phase Shifter with Temperature Compensation for 5G NR Phased-array TransceiverYi Zhang, Jian Pang, Kiyoshi Yanagizawa, Atsushi Shirane, Kenichi Okada. 7-8 [doi]
• An up to 35 dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power SystemsPeter Toth, Hiroki Ishikuro. 9-10 [doi]
• Gate Voltage Optimization in Capacitive DC-DC Converters for Thermoelectric Energy HarvestingYi Tan, Yohsuke Shiiki, Hiroki Ishikuro. 11-12 [doi]
• A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGABo Jiao, Jinshan Zhang, Yuanyuan Xie, Shunli Wang, Haozhe Zhu, Xiaoyang Kang, Zhiyan Dong, Lihua Zhang, Chixiao Chen. 13-14 [doi]
• Supply Noise Reduction Filter for Parallel Integrated Transimpedance AmplifiersShinya Tanimura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine. 15-16 [doi]
• A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoCHai-Dang Vu, Sebastien Le Nours, Sébastien Pillement, Ralf Stemmer, Kim Grüttner. 17-22 [doi]
• Simulation of Ideally Switched Circuits in SystemCBreytner Joseph Fernández-Mesa, Liliana Andrade, Frédéric Pétrot. 23-28 [doi]
• HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large BenchmarksSoowang Park, Jae-Won Nam, Sandeep K. Gupta. 29-34 [doi]
• A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNsChirag Sudarshan, Taha Soliman, Cecilia De la Parra, Christian Weis, Leonardo Ecco, Matthias Jung 0001, Norbert Wehn, Andre Guntoro. 35-42 [doi]
• A Quantized Training Framework for Robust and Accurate ReRAM-based Neural Network AcceleratorsChenguang Zhang, Pingqiang Zhou. 43-48 [doi]
• Attention-in-Memory for Few-Shot Learning with Configurable Ferroelectric FET ArraysDayane Reis, Ann Franchesca Laguna, Michael T. Niemier, Xiaobo Sharon Hu. 49-54 [doi]
• Mutation-based Compliance Testing for RISC-VVladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler. 55-60 [doi]
• A General Equivalence Checking Framework for Multivalued LogicChia-Chun Lin, Hsin-Ping Yen, Sheng-Hsiu Wei, Pei-pei Chen, Yung-Chih Chen, Chun-Yao Wang. 61-66 [doi]
• ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS DesignsMehran Goli, Rolf Drechsler. 67-72 [doi]
• A Multi-Commodity Network Flow Based Routing Algorithm for Paper-Based Digital Microfluidic BiochipsNai-Ren Shih, Tsung-Yi Ho. 73-78 [doi]
• Interference-Free Design Methodology for Paper-Based Digital Microfluidic BiochipsYun-Chen Lo, Bing Li, Sooyong Park, Kwanwoo Shin, Tsung-Yi Ho. 79-84 [doi]
• Accurate and Efficient Simulation of Microfluidic NetworksGerold Fink, Philipp Ebner, Medina Hamidovic, Werner Haselmayr, Robert Wille. 85-90 [doi]
• A 65nm CMOS Process Li-ion Battery Charging Cascode SIDO Boost Converter with 89% Maximum Efficiency for RF Wireless Power Transfer ReceiverYasuaki Isshiki, Dai Suzuki, Ryo Ishida, Kousuke Miyaji. 91-92 [doi]
• A High Accuracy Phase and Amplitude Detection Circuit for Calibration of 28GHz Phased Array Beamformer SystemJoshua Alvin, Jian Pang, Atsushi Shirane, Kenichi Okada. 93-94 [doi]
• A Highly Integrated Energy-efficient CMOS Millimeter-wave Transceiver with Direct-modulation Digital Transmitter, Quadrature Phased-coupled Frequency Synthesizer and Substrate-Integrated Waveguide E-shaped Patch AntennaWei Deng 0001, Zheng Song, Ruichang Ma, Haikun Jia, Baoyong Chi. 95-96 [doi]
• A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOSKota Shiba, Tatsuo Omori, Mototsugu Hamada, Tadahiro Kuroda. 97-98 [doi]
• Sub-10-μm Coil Design for Multi-Hop Inductive Coupling InterfaceTatsuo Omori, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda. 99-100 [doi]
• Current-Starved Chaotic Oscillator Over Multiple Frequency Decades on Low-Cost CMOS: Towards Distributed and Scalable Environmental Sensing with a Myriad of NodesKorkut Kaan Tokgoz, Ludovico Minati, Hiroyuki Ito. 101-102 [doi]
• TCI Tester: Tester for Through Chip InterfaceHideto Kayashima, Hideharu Amano. 103-104 [doi]
• An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle ConceptPeter Toth, Hiroki Ishikuro. 105-106 [doi]
• Connection-based Processing-In-Memory Engine Design Based on Resistive CrossbarsShuhang Zhang, Hai Helen Li, Ulf Schlichtmann. 107-113 [doi]
• FePIM: Contention-Free In-Memory Computing Based on Ferroelectric Field-Effect TransistorsXiaoming Chen 0003, Yuping Wu, Yinhe Han. 114-119 [doi]
• RIME: A Scalable and Energy-Efficient Processing-In-Memory Architecture for Floating-Point OperationsZhaojun Lu, Md Tanvir Arafin, Gang Qu. 120-125 [doi]
• A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADCYuxuan Huang, Yifan He, Jinshan Yue, Huazhong Yang, Yongpan Liu. 126-131 [doi]
• Cross-layer Design for Computing-in-Memory: From Devices, Circuits, to Architectures and ApplicationsHussam Amrouch, Xiaobo Sharon Hu, Mohsen Imani, Ann Franchesca Laguna, Michael T. Niemier, Simon Thomann, Xunzhao Yin, Cheng Zhuo. 132-139 [doi]
• Automatic Surrogate Model Generation and Debugging of Analog/Mixed-Signal Designs Via Collaborative Stimulus Generation and Machine LearningJun-Yang Lei, Abhijit Chatterjee. 140-145 [doi]
• A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local PenalizationJiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng 0001. 146-151 [doi]
• Layout Symmetry Annotation for Analog Circuits with Graph Neural NetworksXiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan, Yibo Lin. 152-157 [doi]
• Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning ModelsTonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar. 158-163 [doi]
• TreeNet: Deep Point Cloud Embedding for Routing Tree ConstructionWei Li, Yuxiao Qu, Gengjie Chen, Yuzhe Ma, Bei Yu 0001. 164-169 [doi]
• A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential PairsTing-Chou Lin, Devon Merrill, Yen-Yi Wu, Chester Holtz, Chung-Kuan Cheng. 170-175 [doi]
• Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing AssignmentDan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young. 176-182 [doi]
• Boosting Pin Accessibility Through Cell Layout Topology DiversificationSuwan Kim, Kyeongrok Jo, Taewhan Kim. 183-188 [doi]
• Approximate Computing for ML: State-of-the-art, Challenges and VisionsGeorgios Zervakis, Hassaan Saadat, Hussam Amrouch, Andreas Gerstlauer, Sri Parameswaran, Jörg Henkel. 189-196 [doi]
• Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router ArchitecturesJan Moritz Joseph, Lennart Bamberg, Geonhwa Jeong, Ruei-Ting Chien, Rainer Leupers, Alberto Garía-Ortiz, Tushar Krishna, Thilo Pionteck. 197-203 [doi]
• Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAsCheng Li, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei. 204-209 [doi]
• A Dynamic Link-latency Aware Cache Replacement Policy (DLRP)Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang. 210-215 [doi]
• Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse SchemeShuxin Zhou, Huandong Wang, Dong Tong. 216-221 [doi]
• Residue-Net: Multiplication-free Neural Network by In-situ No-loss Migration to Residue Number SystemsSahand Salamat, Sumiran Shubhi, Behnam Khaleghi, Tajana Rosing. 222-228 [doi]
• A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI AcceleratingSong Zhang, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei. 229-234 [doi]
• DeepOpt: Optimized Scheduling of CNN Workloads for ASIC-based Systolic Deep Learning AcceleratorsSusmita Dey Manasi, Sachin S. Sapatnekar. 235-241 [doi]
• Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN AcceleratorsJun-Shen Wu, Chi-En Wang, Ren-Shuo Liu. 242-247 [doi]
• MIPAC: Dynamic Input-Aware Accuracy Control for Dynamic Auto-Tuning of Iterative Approximate ComputingTaylor Kemp, Yao Yao, Younghyun Kim. 248-253 [doi]
• Normalized Stability: A Cross-Level Design Metric for Early Termination in Stochastic ComputingDi Wu, Ruokai Yin, Joshua San Miguel. 254-259 [doi]
• Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic ComputingHsuan Hsiao, Joshua San Miguel, Yuko Hara-Azumi, Jason Helge Anderson. 260-265 [doi]
• An Efficient Approximate Node Merging with an Error Rate GuaranteeKit Seng Tam, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang. 266-271 [doi]
• An Adaptive Delay Model for Timing Yield Estimation under Wide-Voltage RangeHao Yan, Xiao Shi, Chengzhen Xuan, Peng Cao 0002, Longxing Shi. 272-277 [doi]
• ATM: A High Accuracy Extracted Timing Model for Hierarchical Timing AnalysisKuan-Ming Lai, Tsung-Wei Huang, Pei-Yu Lee, Tsung-Yi Ho. 278-283 [doi]
• Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy MinimizationTaiYu Cheng, Yukata Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto. 284-290 [doi]
• A Timing Prediction Framework for Wide Voltage Design with Data Augmentation StrategyPeng Cao, Wei Bao, Kai Wang, Tai Yang. 291-296 [doi]
• Energy-Efficient Deep Neural Networks with Mixed-Signal Neurons and Dense-Local and Sparse-Global ConnectivityBaibhab Chatterjee, Shreyas Sen. 297-304 [doi]
• Merged Logic and Memory Fabrics for AI WorkloadsBrian Crafton, Samuel Spetalnick, Arijit Raychowdhury. 305-310 [doi]
• Vision Control Unit in Fully Self Driving Vehicles using Xilinx MPSoC and Opensource StackRavikumar V. Chakaravarthy, Hyun Kwon, Hua Jiang. 311-317 [doi]
• Constrained Conservative State Symbolic Co-analysis for Ultra-low-power Embedded SystemsShashank Hegde, Subhash Sethumurugan, Hari Cherupalli, Henry Duwe, John Sartori. 318-324 [doi]
• Arbitrary and Variable Precision Floating-Point Arithmetic Support in Dynamic Binary TranslationMarie Badaroux, Frédéric Pétrot. 325-330 [doi]
• Optimizing Temporal Decoupling using Event RelevanceLukas Jünger 0001, Carmine Bianco, Kristof Niederholtmeyer, Dietmar Petras, Rainer Leupers. 331-337 [doi]
• Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter OptimizationThanh Cong, François Charot. 338-343 [doi]
• DNR: A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNsSouvik Kundu, Mahdi Nazemi, Peter A. Beerel, Massoud Pedram. 344-350 [doi]
• Dynamic Programming Assisted Quantization Approaches for Compressing Normal and Robust DNN ModelsDingcheng Yang, Wenjian Yu, Haoyuan Mu, Gary Yao. 351-357 [doi]
• Accelerate Non-unit Stride Convolutions with Winograd AlgorithmsJunhao Pan, Deming Chen. 358-364 [doi]
• Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error ModellingCecilia De la Parra, Andre Guntoro, Akash Kumar 0001. 365-371 [doi]
• Mixed Precision Quantization for ReRAM-based DNN Inference AcceleratorsSitao Huang, Aayush Ankit, Plinio Silveira, Rodrigo Antunes, Sai Rahul Chalamalasetti, Izzat El Hajj, Dong Eun Kim, Glaucimar Aguiar, Pedro Bruel, Sergey Serebryakov, Cong Xu, Can Li, Paolo Faraboschi, John Paul Strachan, Deming Chen, Kaushik Roy 0001, Wen-mei W. Hwu, Dejan S. Milojicic. 372-377 [doi]
• A reduced-precision streaming SpMV architecture for Personalized PageRank on FPGAAlberto Parravicini, Francesco Sgherzi, Marco D. Santambrogio. 378-383 [doi]
• HyperRec: Efficient Recommender Systems with Hyperdimensional ComputingYunhui Guo, Mohsen Imani, Jaeyoung Kang, Sahand Salamat, Justin Morris, Baris Aksanli, Yeseong Kim, Tajana Rosing. 384-389 [doi]
• Efficient Techniques for Training the Memristor-based Spiking Neural Networks Targeting Better Speed, Energy and LifetimeYu Ma, Pingqiang Zhou. 390-395 [doi]
• PCBench: Benchmarking of Board-Level Hardware Attacks and TrojansHuifeng Zhu, Xiaolong Guo, Yier Jin, Xuan Zhang 0001. 396-401 [doi]
• Cache-Aware Dynamic Skewed Tree for Fast Memory AuthenticationSaru Vig, Siew Kei Lam, Rohan Juneja. 402-407 [doi]
• Automated Test Generation for Hardware Trojan Detection using Reinforcement LearningZhixin Pan, Prabhat Mishra 0001. 408-413 [doi]
• On the Impact of Aging on Power Analysis Attacks Targeting Power-Equalized Cryptographic CircuitsMd Toufiq Hasan Anik, Bijan Fadaeinia, Amir Moradi 0001, Naghmeh Karimi. 414-420 [doi]
• Energy-Performance Co-Management of Mixed-Sensitivity Workloads on Heterogeneous Multi-core SystemsElham Shamsa, Anil Kanduri, Amir M. Rahmani, Pasi Liljeberg. 421-427 [doi]
• Optimizing Inter-Core Data-Propagation Delays in Industrial Embedded Systems under Partitioned SchedulingLamija Hasanagic, Tin Vidovic, Saad Mubeen, Mohammad Ashjaei, Matthias Becker 0004. 428-434 [doi]
• LiteIndex: Memory-Efficient Schema-Agnostic Indexing for JSON documents in SQLiteSiqi Shang, Qihong Wu, Tianyu Wang, Zili Shao. 435-440 [doi]
• Micro-architectural Cache Side-Channel Attacks and CountermeasuresChaoqun Shen, Congcong Chen, Jiliang Zhang 0002. 441-448 [doi]
• Security of Neural Networks from Hardware Perspective: A Survey and BeyondQian Xu, Md Tanvir Arafin, Gang Qu. 449-454 [doi]
• Learning Assisted Side Channel Delay Test for Detection of Recycled ICsAshkan Vakil, Farzad Niknia, Ali Mirzaeian, Avesta Sasan, Naghmeh Karimi. 455-462 [doi]
• ML-augmented Methodology for Fast Thermal Side-channel Emission AnalysisNorman Chang, Deqi Zhu, Lang Lin, Dinesh Selvakumaran, Jimin Wen, Stephen H. Pan, Wenbo Xia, Hua Chen, Calvin Chow, Gary Chen. 463-468 [doi]
• 1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification MethodLi-Cheng Zheng, Hao-Ju Chang, Yung-Chih Chen, Jing-Yang Jou. 469-474 [doi]
• A Novel Technology Mapper for Complex Universal GatesMeng-Che Wu, Ai Quoc Dao, Mark Po-Hung Lin. 475-480 [doi]
• High-Level Synthesis of Transactional MemoryOmar Ragheb, Jason Helge Anderson. 481-486 [doi]
• VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial AttackHao Lv, Bing Li, Ying Wang, Cheng Liu, Lei Zhang. 487-492 [doi]
• Entropy-Based Modeling for Estimating Adversarial Bit-flip Attack Impact on Binarized Neural NetworkNavid Khoshavi, Saman Sargolzaei, Yu Bi, Arman Roohi. 493-498 [doi]
• A Low Cost Weight Obfuscation Scheme for Security Enhancement of ReRAM Based Neural Network AcceleratorsYuhang Wang, Song Jin, Tao Li. 499-504 [doi]
• Puncturing the memory wall: Joint optimization of network compression with approximate memory for ASR applicationQin Li 0016, Peiyan Dong, Zijie Yu, Changlu Liu, Fei Qiao, Yanzhi Wang, Huazhong Yang. 505-511 [doi]
• Canonical Huffman Decoder on Fine-grain Many-core Processor ArraysSatyabrata Sarangi, Bevan Baas. 512-517 [doi]
• A Decomposition-Based Synthesis Algorithm for Sparse Matrix-Vector Multiplication in Parallel Communication StructureMingfei Yu, Ruitao Gao, Masahiro Fujita. 518-523 [doi]
• Learning Boolean Circuits from Examples for Approximate Logic SynthesisSina Boroumand, Christos-Savvas Bouganis, George A. Constantinides. 524-529 [doi]
• Read your Circuit: Leveraging Word Embedding to Guide Logic OptimizationWalter Lau Neto, Matheus Trevisan Moreira, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon. 530-535 [doi]
• Exploiting HLS-Generated Multi-Version Kernels to Improve CPU-FPGA Cloud SystemsBernardo Neuhaus Lignati, Michael Guilherme Jordan, Guilherme Korol, Mateus Beck Rutzig, Antonio Carlos Schneider Beck. 536-541 [doi]
• Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable ArchitecturesJianqi Chen, Benjamin Carrión Schäfer. 542-547 [doi]
• ObfusX: Routing Obfuscation with Explanatory Analysis of a Machine Learning AttackWei Zeng 0015, Azadeh Davoodi, Rasit Onur Topaloglu. 548-554 [doi]
• Breaking Analog Biasing Locking Techniques via Re-SynthesisJulian Leonhard, Mohamed Elshamy, Marie-Minerve Louërat, Haralampos-G. D. Stratigopoulos. 555-560 [doi]
• Energy and QoS-Aware Dynamic Reliability Management of IoT Edge Computing SystemsKazim Ergun, Raid Ayoub, Pietro Mercati, Dancheng Liu, Tajana Rosing. 561-567 [doi]
• Light: A Scalable and Efficient Wavelength-Routed Optical Networks-On-Chip TopologyZhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann. 568-573 [doi]
• One-pass Synthesis for Field-coupled Nanocomputing TechnologiesMarcel Walter, Winston Haaswijk, Robert Wille, Frank Sill Torres, Rolf Drechsler. 574-580 [doi]
• Real-Time Mobile Acceleration of DNNs: From Computer Vision to Medical ApplicationsHongjia Li, Geng Yuan, Wei Niu, Yuxuan Cai, Mengshu Sun, Zhengang Li, Bin Ren, Xue Lin, Yanzhi Wang. 581-586 [doi]
• Dynamic Neural Network to Enable Run-Time Trade-off between Accuracy and LatencyLi Yang, Deliang Fan. 587-592 [doi]
• When Machine Learning Meets Quantum Computers: A Case StudyWeiwen Jiang, Jinjun Xiong, Yiyu Shi. 593-598 [doi]
• Improving Efficiency in Neural Network Accelerator using Operands Hamming Distance OptimizationMeng Li 0004, Yilei Li, Vikas Chandra. 599-604 [doi]
• Lightweight Run-Time Working Memory Compression for Deployment of Deep Neural Networks on Resource-Constrained MCUsZhepeng Wang, Yawen Wu, Zhenge Jia, Yiyu Shi, Jingtong Hu. 607-614 [doi]
• EHDSktch: A Generic Low Power Architecture for Sketching in Energy Harvesting DevicesPriyanka Singla, Chandran Goodchild, Smruti R. Sarangi. 615-620 [doi]
• Energy-Aware Design Methodology for Myocardial Infarction Detection on Low-Power Wearable DevicesMohanad Odema, Nafiul Rashid, Mohammad Abdullah Al Faruque. 621-626 [doi]
• Power-Efficient Layer Mapping for CNNs on Integrated CPU and GPU Platforms: A Case StudyTian Wang, Kun Cao, Junlong Zhou, Gongxuan Zhang, Xiji Wang. 627-632 [doi]
• A Write-friendly Arithmetic Coding Scheme for Achieving Energy-Efficient Non-Volatile Memory SystemsYi-Shen Chen, Chun-Feng Wu, Yuan-Hao Chang 0001, Tei-Wei Kuo. 633-638 [doi]
• DP-Sim: A Full-stack Simulation Infrastructure for Digital Processing In-Memory ArchitecturesMinxuan Zhou, Mohsen Imani, Yeseong Kim, Saransh Gupta, Tajana Rosing. 639-644 [doi]
• SAC: A Stream Aware Write Cache Scheme for Multi-Streamed Solid State DrivesBo Zhou, Chuanming Ding, Yina Lv, Chun Jason Xue, Qingfeng Zhuge, Edwin H.-M. Sha, Liang Shi. 645-650 [doi]
• Providing Plug N' Play for Processing-in-Memory AcceleratorsPaulo C. Santos, Bruno E. Forlin, Luigi Carro. 651-656 [doi]
• Aging-Aware Request Scheduling for Non-Volatile Main MemoryShihao Song, Anup Das 0001, Onur Mutlu, Nagarajan Kandasamy. 657-664 [doi]
• Placement for Wafer-Scale Deep Learning AcceleratorBenzheng Li, Qi Du, Dingcheng Liu, Jingchong Zhang, Gengjie Chen, Hailong You. 665-670 [doi]
• Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length EstimationZhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, Yiran Chen. 671-677 [doi]
• Machine Learning-based Structural Pre-route Insertability Prediction and Improvement with Guided BackpropagationTao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Chin-Hsiung Hsu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen. 678-683 [doi]
• Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology NodesHaoxing Ren, Matthew Fojtik. 684-689 [doi]
• Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder NetworksVidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar. 690-696 [doi]
• GRA-LPO: Graph Convolution Based Leakage Power OptimizationUday Mallappa, Chung-Kuan Cheng. 697-702 [doi]
• DEF: Differential Encoding of Featuremaps for Low Power Convolutional Neural Network AcceleratorsAlexander Montgomerie-Corcoran, Christos-Savvas Bouganis. 703-708 [doi]
• Temperature-Aware Optimization of Monolithic 3D Deep Neural Network AcceleratorsPrachi Shukla, Sean S. Nemtzow, Vasilis F. Pavlidis, Emre Salman, Ayse K. Coskun. 709-714 [doi]
• Gravity: An Artificial Neural Network Compiler for Embedded ApplicationsTony Givargis. 715-721 [doi]
• A Self-Test Framework for Detecting Fault-induced Accuracy Drop in Neural Network AcceleratorsFanruo Meng, Fateme S. Hosseini, Chengmo Yang. 722-727 [doi]
• Facilitating the Efficiency of Secure File Data and Metadata Deletion on SMR-based Ext4 File SystemPing-Xiang Chen, Shuo-Han Chen, Yuan-Hao Chang 0001, Yu-Pei Liang, Wei Kuan Shih. 728-733 [doi]
• Efficient Computing Platform Design for Autonomous Driving SystemsShuang Liang, Changcheng Tang, Xuefei Ning, Shulin Zeng, Jincheng Yu, Yu Wang 0002, Kaiyuan Guo, Diange Yang, Tianyi Lu, Huazhong Yang. 734-741 [doi]
• On Designing Computing Systems for Autonomous Vehicles: a PerceptIn Case StudyBo Yu, Jie Tang 0003, Shaoshan Liu. 742-747 [doi]
• Runtime Software Selection for Adaptive Automotive SystemsChia-Ching Fu, Ben-Hau Chia, Chung-Wei Lin. 748-752 [doi]
• Safety-Assured Design and Adaptation of Learning-Enabled Autonomous SystemsQi Zhu 0002, Chao Huang, Ruochen Jiao, Shuyue Lan, Hengyi Liang, Xiangguo Liu, Yixuan Wang, Zhilu Wang, Shichao Xu. 753-760 [doi]
• System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic RelationsMuhammad Hassan 0002, Daniel Große, Rolf Drechsler. 761-766 [doi]
• Random Stimuli Generation for the Verification of Quantum CircuitsLukas Burgholzer, Richard Kueng, Robert Wille. 767-772 [doi]
• Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit ModelsChrysostomos Chatzigeorgiou, Dimitrios Garyfallou, George Floros 0002, Nestor E. Evmorfopoulos, George I. Stamoulis. 773-778 [doi]
• Algebraic and Boolean Optimization Methods for AQFP Superconducting CircuitsEleonora Testa, Siang-Yun Lee, Heinz Riener, Giovanni De Micheli. 779-785 [doi]
• Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor ArchitecturesAtsushi Matsuo, Wakaki Hattori, Shigeru Yamashita. 786-791 [doi]
• Exploiting Quantum Teleportation in Quantum Circuit MappingStefan Hillmich, Alwin Zulehner, Robert Wille. 792-797 [doi]
• Hardware-Aware NAS Framework with Layer Adaptive Scheduling on Embedded SystemChuxi Li, Xiaoya Fan, Shengbing Zhang, Zhao Yang, Miao Wang, Danghui Wang, Meng Zhang. 798-805 [doi]
• Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-PackageRobert Guirado, Hyoukjun Kwon, Sergi Abadal, Eduard Alarcón, Tushar Krishna. 806-812 [doi]
• Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT ModulesYifan He, Jinshan Yue, Yongpan Liu, Huazhong Yang. 813-818 [doi]
• BatchSizer: Power-Performance Trade-off for DNN InferenceSeyed Morteza Nabavinejad, Sherief Reda, Masoumeh Ebrahimi. 819-824 [doi]
• Deep Learning for Mask Synthesis and Verification: A SurveyYibo Lin. 825-832 [doi]
• Physical Synthesis for Advanced Neural Network ProcessorsZhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, Yibo Lin, Bei Yu 0001. 833-840 [doi]
• Advancements and Challenges on Parasitic Extraction for Advanced Process TechnologiesWenjian Yu, Mingye Song, Ming Yang. 841-846 [doi]
• Reliability-Aware Training and Performance Modeling for Processing-In-Memory SystemsHanbo Sun, Zhenhua Zhu, Yi Cai, Shulin Zeng, Kaizhong Qiu, Yu Wang, Huazhong Yang. 847-852 [doi]
• Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural NetworksGrace Li Zhang, Bing Li 0005, Ying Zhu, Tianchen Wang, Yiyu Shi, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Tsung-Yi Ho, Ulf Schlichtmann. 853-858 [doi]
• Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture SearchZheyu Yan, Da-Cheng Juan, Xiaobo Sharon Hu, Yiyu Shi. 859-864 [doi]
• A Physical-Aware Framework for Memory Network Design Space ExplorationTianhao Shen, Di Gao, Li Zhang 0021, Jishen Zhao, Cheng Zhuo. 865-871 [doi]
• Manufacturing-Aware Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement RefinementYu-Jin Xie, Kuan-Yu Chen, Wai-Kei Mak. 872-877 [doi]
• A Hierarchical Assessment Strategy on Soft Error Propagation in Deep Learning ControllerTing Liu, Yuzhuo Fu, Yan Zhang, Bin Shi. 878-884 [doi]
• Attacking a CNN-based Layout Hotspot Detector Using Group Gradient MethodHaoyu Yang, Shifan Zhang, Kang Liu 0017, Siting Liu, Benjamin Tan, Ramesh Karri, Siddharth Garg, Bei Yu 0001, Evangeline F. Y. Young. 885-891 [doi]
• Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated CircuitsZhengqi Gao, Zihao Chen, Jun Tao 0001, Yangfeng Su, Dian Zhou, Xuan Zeng 0001. 892-897 [doi]
• Analog IC Aging-induced Degradation Estimation via Heterogeneous Graph Convolutional NetworksTinghuan Chen, Qi Sun, Canhui Zhan, Changze Liu, Huatao Yu, Bei Yu 0001. 898-903 [doi]