Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability

Wei Hwang, George Diedrich Gristede, Pia Sanda, Shao Y. Wang, David F. Heidel. Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability. J. Solid-State Circuits, 34(8):1108-1117, 1999. [doi]

Abstract

Abstract is missing.