Abstract is missing.
- Architectural Support for the Stream Execution Model on General-Purpose ProcessorsJayanth Gummaraju, Mattan Erez, Joel Coburn, Mendel Rosenblum, William J. Dally. 3-12 [doi]
- A Flexible Heterogeneous Multi-Core ArchitectureMiquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero. 13-24 [doi]
- Improving Performance Isolation on Chip Multiprocessors via an Operating System SchedulerAlexandra Fedorova, Margo I. Seltzer, Michael D. Smith. 25-38 [doi]
- Software-Pipelining on Multi-Core ArchitecturesAlban Douillet, Guang R. Gao. 39-48 [doi]
- Speculative Decoupled Software PipeliningNeil Vachharajani, Ram Rangan, Easwaran Raman, Matthew J. Bridges, Guilherme Ottoni, David I. August. 49-59 [doi]
- Rotating Register Allocation for Enhanced Pipeline SchedulingSuhyun Kim, Soo-Mook Moon. 60-72 [doi]
- Unified Architectural Support for Soft-Error Protection or Software Bug DetectionMartin Dimitrov, Huiyang Zhou. 73-82 [doi]
- Verification-Aware Microprocessor DesignAnita Lungu, Daniel J. Sorin. 83-93 [doi]
- I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor SystemsManhee Lee, Minseon Ahn, Eun Jung Kim. 94-103 [doi]
- Error Detection Using Dynamic Dataflow VerificationAlbert Meixner, Daniel J. Sorin. 104-118 [doi]
- Extending Object-Oriented Optimizations for Concurrent ProgramsKelly Heffner, David Tarditi, Michael D. Smith. 119-129 [doi]
- Language and Virtual Machine Support for Efficient Fine-Grained Futures in JavaLingli Zhang, Chandra Krintz, Priya Nagpurkar. 130-139 [doi]
- Call-chain Software Instruction Prefetching in J2EE Server ApplicationsPriya Nagpurkar, Harold W. Cain, Mauricio J. Serrano, Jong-Deok Choi, Chandra Krintz. 140-149 [doi]
- Detecting Change in Program Behavior for Adaptive OptimizationNitzan Peleg, Bilha Mendelson. 150-162 [doi]
- Reducing Energy Consumption of On-Chip Networks Through a Hybrid Compiler-Runtime ApproachGuangyu Chen, Feihui Li, Mahmut T. Kandemir. 163-174 [doi]
- An Energy Efficient Parallel Architecture Using Near Threshold OperationRonald G. Dreslinski, Bo Zhai, Trevor N. Mudge, David Blaauw, Dennis Sylvester. 175-188 [doi]
- AA-Sort: A New Parallel Sorting Algorithm for Multi-Core SIMD ProcessorsHiroshi Inoue, Takao Moriyama, Hideaki Komatsu, Toshio Nakatani. 189-198 [doi]
- The Fault Tolerant Parallel Algorithm: the Parallel Recomputing Based Failure RecoveryXuejun Yang, Yunfei Du, Panfeng Wang, Hongyi Fu, Jia Jia, Zhiyuan Wang, Guang Suo. 199-212 [doi]
- Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core OverclockingBrian Greskamp, Josep Torrellas. 213-224 [doi]
- Early Register Release for Out-of-Order Processors with RegisterWindowsEduardo Quiñones, Joan-Manuel Parcerisa, Antonio González. 225-234 [doi]
- L1 Cache Filtering Through Random Selection of Memory ReferencesYoav Etsion, Dror G. Feitelson. 235-244 [doi]
- Effective Management of DRAM Bandwidth in Multicore ProcessorsNauman Rafique, Won-Taek Lim, Mithuna Thottethodi. 245-258 [doi]
- A Loop Correlation Technique to Improve Performance AuditingJeremy Lau, Matthew Arnold, Michael Hind, Brad Calder. 259-269 [doi]
- Latency Hiding in Multi-Threading and Multi-Processing of Network ApplicationsXiaofeng Guo, Jinquan Dai, Long Li, Zhiyuan Lv, Prashant R. Chandra. 270-279 [doi]
- Introducing Control Flow into Vectorized CodeJaewook Shin. 280-291 [doi]
- Automatic Correction of Loop TransformationsNicolas Vasilache, Albert Cohen, Louis-Noël Pouchet. 292-304 [doi]
- FAME: FAirly MEasuring Multithreaded ArchitecturesJavier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero. 305-316 [doi]
- CIGAR: Application Partitioning for a CPU/Coprocessor ArchitectureJohn H. Kelm, Isaac Gelado, Mark J. Murphy, Nacho Navarro, Steven S. Lumetta, Wen-mei W. Hwu. 317-326 [doi]
- Using PredictiveModeling for Cross-Program Design Space Exploration in Multicore SystemsSalman Khan, Polychronis Xekalakis, John Cavazos, Marcelo Cintra. 327-338 [doi]
- CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP PlatformsLi Zhao, Ravi R. Iyer, Ramesh Illikkal, Jaideep Moses, Srihari Makineni, Donald Newell. 339-352 [doi]
- Component-Based Lock AllocationRichard L. Halpert, Christopher J. F. Pickett, Clark Verbrugge. 353-364 [doi]
- JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional MemoryMarek Olszewski, Jeremy Cutler, J. Gregory Steffan. 365-375 [doi]
- The OpenTM Transactional Application Programming InterfaceWoongki Baek, Chi Cao Minh, Martin Trautmann, Christos Kozyrakis, Kunle Olukotun. 376-387 [doi]
- A Study of a Transactional Parallel Routing AlgorithmIan Watson, Chris C. Kirkham, Mikel Luján. 388-398 [doi]
- Ring Prediction for Non-Uniform Cache ArchitecturesSayaka Akioka, Feihui Li, Mahmut T. Kandemir, Padma Raghavan, Mary Jane Irwin. 401 [doi]
- Source Level Merging of Independent ProgramsYosi Ben-Asher, Moshe Yuda. 402 [doi]
- Studying the impact of synchronization frequency on scheduling tasks with dependencies in heterogeneous systemsFlorina M. Ciorba, Ioannis Riakiotakis, George K. Papakonstantinou, Theodore Andronikos, Anthony T. Chronopoulos. 403 [doi]
- Fast prototyping of complex Signal and Image Processing applications on SoC using homogenous network of communicating processorsLionel Damez, Jean-Pierre Dérutin. 404 [doi]
- Stream Scheduling: A Framework to Manage Bulk Operations in a Memory HierarchyAbhishek Das, William J. Dally. 405 [doi]
- Studying Compiler-Microarchitecture Interactions through Interval AnalysisStijn Eyerman, Lieven Eeckhout, James E. Smith. 406 [doi]
- FastForward for Efficient Pipeline ParallelismJohn Giacomoni, Tipp Moseley, Manish Vachharajani. 407 [doi]
- The Automatic Transformation of Linked List Data StructuresSven Groot, Harmen L. A. van der Spek, Erwin M. Bakker, Harry A. G. Wijshoff. 408 [doi]
- Trace-based Automatic Padding for Locality Improvement with Correlative Data Visualization InterfaceMarco Höbbel, Thomas Rauber, Carsten Scholtes. 409 [doi]
- A New Parallel Gauss-Seidel Method by Iteration Space Alternate TilingChangjun Hu, Jilin Zhang, Jue Wang, Jianjiang Li, Liang Ding. 410 [doi]
- Performance Portable Optimizations for Loops Containing Communication OperationsCostin Iancu, Wei Chen, Katherine A. Yelick. 411 [doi]
- Exploring the Application Behavior Space Using Parameterized Synthetic BenchmarksAjay M. Joshi, Lieven Eeckhout, Lizy Kurian John. 412 [doi]
- Studying Asynchronous Shared Memory ComputationsSimo Juvaste. 413 [doi]
- Fast Track: Supporting Unsafe Optimizations with Software SpeculationKirk Kelsey, Chengliang Zhang, Chen Ding. 414 [doi]
- Hybrid Specialization: A Trade-off Between Static and Dynamic SpecializationMinhaj Ahmad Khan, Henri-Pierre Charles, Denis Barthou. 415 [doi]
- Rate-Driven Control of Resizable Caches for Highly Threaded SMT ProcessorsSonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares. 416 [doi]
- Redesigning Parallel Symbolic Computations PackagesGeorgiana Macariu, Marc Frîncu, Alexandru Cârstea, Dana Petcu, Andrei Eckstein. 417 [doi]
- MLP-Aware Dynamic Cache PartitioningMiquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero. 418 [doi]
- A Lightweight Model for Software Thread-Level Speculation (TLS)Cosmin E. Oancea, Alan Mycroft. 419 [doi]
- HelperCore_DB: Exploiting Multicore Technology for DatabasesKostas Papadopoulos, Kyriakos Stavrou, Pedro Trancoso. 420 [doi]
- Data Structure Exploration of Dynamic ApplicationsLazaros Papadopoulos, Christos Baloukas, Dimitrios Soudris, Konstantinos Potamianos, N. Voros. 421 [doi]
- Dynamic Cache Placement with Two-level Mapping to Reduce Conflict MissesKaushik Rajan, R. Govindarajan, Bharadwaj Amrutur. 422 [doi]
- Runahead Threads: Reducing Resource Contention in SMT ProcessorsTanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero. 423 [doi]
- Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource AllocationBogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, Sule Ozev. 424 [doi]
- Drug Design on the Cell BroadBand EngineHarald Servat, Cecilia Gonzalez, Xavier Aguilar, Daniel Cabrera, Daniel Jimenez. 425 [doi]
- Bridging Inputs and Program Dynamic BehaviorXipeng Shen, Feng Mao. 426 [doi]
- Power-Aware Compiler Controllable Chip MultiprocessorHiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara. 427 [doi]
- RSTM : A Relaxed Consistency Software Transactional Memory for MulticoresJaswanth Sreeram, Romain Cledat, Tushar Kumar, Santosh Pande. 428 [doi]
- VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded ProcessorsRafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato. 429 [doi]
- A Scalable Low Power Store Queue for Large InstructionWindow ProcessorsRajesh Vivekanandham, R. Govindarajan. 430 [doi]
- Adapting to Intermittent Faults in Future Multicore SystemsPhilip M. Wells, Koushik Chakraborty, Gurindar S. Sohi. 431 [doi]
- A Phase-Adaptive Approach to Increasing Cache PerformanceMatthew A. Watkins, Sally A. McKee, Lambert Schaelicke. 432 [doi]
- Compiler Optimizations for Fault Tolerance Software CheckingJing Yu, María Jesús Garzarán. 433 [doi]
- Optimizing Bandwidth Constraint through Register Interconnection for Stream ProcessorsWeihua Zhang, Tao Bao, Binyu Zang, Chuanqi Zhu. 434 [doi]