Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization

Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. IEICE Transactions, 88-A(7):1957-1963, 2005. [doi]

Authors

Tetsuya Iizuka

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Makoto Ikeda

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Kunihiro Asada

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