Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization

Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. IEICE Transactions, 88-A(7):1957-1963, 2005. [doi]

Abstract

Abstract is missing.