A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems - researchr publication authors

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Shinichi Ikeda, Akira Iwata, Goichi Otomo, Tomoaki Suzuki, Hiroaki Iijima, Mikio Shiraishi, Shinya Kawakami, Masatomo Eimitsu, Yoshiki Matsuoka, Kiyohito Sato, Shigehiro Tsuchiya, Yoshinori Shigeta, Takuma Aoyama. A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2023, Haikou, China, November 5-8, 2023. pages 1-3, IEEE, 2023. [doi]

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