A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems

Shinichi Ikeda, Akira Iwata, Goichi Otomo, Tomoaki Suzuki, Hiroaki Iijima, Mikio Shiraishi, Shinya Kawakami, Masatomo Eimitsu, Yoshiki Matsuoka, Kiyohito Sato, Shigehiro Tsuchiya, Yoshinori Shigeta, Takuma Aoyama. A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2023, Haikou, China, November 5-8, 2023. pages 1-3, IEEE, 2023. [doi]

@inproceedings{IkedaIOSISKEMSTSA23,
  title = {A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems},
  author = {Shinichi Ikeda and Akira Iwata and Goichi Otomo and Tomoaki Suzuki and Hiroaki Iijima and Mikio Shiraishi and Shinya Kawakami and Masatomo Eimitsu and Yoshiki Matsuoka and Kiyohito Sato and Shigehiro Tsuchiya and Yoshinori Shigeta and Takuma Aoyama},
  year = {2023},
  doi = {10.1109/A-SSCC58667.2023.10348001},
  url = {https://doi.org/10.1109/A-SSCC58667.2023.10348001},
  researchr = {https://researchr.org/publication/IkedaIOSISKEMSTSA23},
  cites = {0},
  citedby = {0},
  pages = {1-3},
  booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2023, Haikou, China, November 5-8, 2023},
  publisher = {IEEE},
  isbn = {979-8-3503-3003-8},
}