Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi. A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. In 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada. pages 269-274, IEEE Computer Society, 2004. [doi]
@inproceedings{InokawaTDAH04,
title = {A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions},
author = {Hiroshi Inokawa and Yasuo Takahashi and Katsuhiko Degawa and Takafumi Aoki and Tatsuo Higuchi},
year = {2004},
url = {http://csdl.computer.org/comp/proceedings/ismvl/2004/2130/00/21300269abs.htm},
tags = {logic, design},
researchr = {https://researchr.org/publication/InokawaTDAH04},
cites = {0},
citedby = {0},
pages = {269-274},
booktitle = {34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada},
publisher = {IEEE Computer Society},
isbn = {0-7695-2130-4},
}