A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, K. Yanagisawa. A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. J. Solid-State Circuits, 46(11):2535-2544, 2011. [doi]

@article{IshiiFTTNKY11,
  title = {A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues},
  author = {Yuichiro Ishii and Hidehiro Fujiwara and Shinji Tanaka and Yasumasa Tsukamoto and Koji Nii and Yuji Kihara and K. Yanagisawa},
  year = {2011},
  doi = {10.1109/JSSC.2011.2164021},
  url = {http://dx.doi.org/10.1109/JSSC.2011.2164021},
  researchr = {https://researchr.org/publication/IshiiFTTNKY11},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {46},
  number = {11},
  pages = {2535-2544},
}