Yousef Iskander, Stephen D. Craven, Athira Chandrasekharan, Sureshwar Rajagopalan, Guruprasad Subbarayan, Tannous Frangieh, Cameron Patterson. Using partial reconfiguration and high-level models to accelerate FPGA design validation. In Jinian Bian, Qiang Zhou, Peter Athanas, Yajun Ha, Kang Zhao, editors, Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China. pages 341-344, IEEE, 2010. [doi]
Abstract is missing.