Table of Contents

• Technology issues facing the world s largest integrated circuitsStephen Brown. [doi]
• Reconfigurable computing - evolution of Von Neumann architectureShaojun Wei. [doi]
• FPGA platforms leading the way in the application of more than Moore s technologyIvo Bolsens. [doi]
• In search for better silicon and human efficiencyAlbert Wang. [doi]
• An FPGA architecture supporting dynamically controlled power gatingAssem A. M. Bsoul, Steven J. E. Wilton. 1-8 [doi]
• A tiled programmable fabric using QCARajeswari Devadoss, Kolin Paul, M. Balakrishnan. 9-16 [doi]
• Phase-change-memory-based storage elements for configurable logicPierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Marina Reyboz, Giovanni Beneventi, Fabien Clermidy, Luca Perniola, Ian O Connor. 17-20 [doi]
• Dynamic reconfigurable bit-parallel architecture for large-scale regular expression matchingYusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga. 21-28 [doi]
• Impact of reconfigurable hardware on accelerating MPI_ReduceShanyuan Gao, Andrew G. Schmidt, Ron Sass. 29-36 [doi]
• Accelerating HMMER on FPGA using parallel prefixes and reductionsNaeem Abbas, Steven Derrien, Sanjay V. Rajopadhye, Patrice Quinton. 37-44 [doi]
• Multiple data set reduction on FPGAsYi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris. 45-52 [doi]
• Accelerating FPGA development through the automatic parallel application of standard implementation toolsAthira Chandrasekharan, Sureshwar Rajagopalan, Guruprasad Subbarayan, Tony Frangieh, Yousef Iskander, Stephen D. Craven, Cameron Patterson. 53-60 [doi]
• Parallelizing FPGA placement using Transactional MemorySteven Birk, J. Gregory Steffan, Jason Helge Anderson. 61-69 [doi]
• A message-passing multi-softcore architecture on FPGA for Breadth-first SearchQingbo Wang, Weirong Jiang, Yinglong Xia, Viktor K. Prasanna. 70-77 [doi]
• Deterministic multi-core parallel routing for FPGAsMarcel Gort, Jason Helge Anderson. 78-86 [doi]
• The TransC process model and interprocess communicationHenning Manteuffel, Cem Savas Bassoy, Friedrich Mayer-Lindenberg. 87-93 [doi]
• Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computingBrahim Betkaoui, David B. Thomas, Wayne Luk. 94-101 [doi]
• Local-and-global stall mechanism for systolic computational-memory array on extensible multi-FPGA systemLuzhou Wang, Kentaro Sano, Satoru Yamamoto. 102-109 [doi]
• Floating-point exponential functions for DSP-enabled FPGAsFlorent de Dinechin, Bogdan Pasca. 110-117 [doi]
• Modular design of fully pipelined accumulatorsMiaoqing Huang, David L. Andrews. 118-125 [doi]
• Efficient implementation of parallel BCD multiplication in LUT-6 FPGAsÁlvaro Vázquez, Florent de Dinechin. 126-133 [doi]
• High performance and memory efficient implementation of matrix multiplication on FPGAsGuiming Wu, Yong Dou, Miao Wang. 134-137 [doi]
• Fine-grained characterization of process variation in FPGAsHaile Yu, Qiang Xu, Philip Heng Wai Leong. 138-145 [doi]
• A stochastic method for security evaluation of cryptographic FPGA implementationsMichael Kasper, Werner Schindler, Marc Stöttinger. 146-153 [doi]
• Fine-grain fault diagnosis for FPGA logic blocksStavros Tzilis, Ioannis Sourdis, Georgi Gaydadjiev. 154-161 [doi]
• A robust reconfigurable logic device based on less configuration memory logic cellQian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi. 162-169 [doi]
• Compact implementations of BLAKE-32 and BLAKE-64 on FPGAJean-Luc Beuchat, Eiji Okamoto, Teppei Yamazaki. 170-177 [doi]
• Lightweight DPA resistant solution on FPGA to counteract power modelsYingxi Lu, Keanhong Boey, Philip Hodgers, Máire O Neill. 178-183 [doi]
• An FPGA-based text search engine for approximate regular expression matchingYuichiro Utan, Shin ichi Wakabayashi, Shinobu Nagayama. 184-191 [doi]
• Real-time detection of line segments on FPGAJianyun Zhu, Tsutomu Maruyama. 192-199 [doi]
• True random number generation in block memories of reconfigurable devicesTim Güneysu. 200-207 [doi]
• Obstacle-free two-dimensional online-routing for run-time reconfigurable FPGA-based systemsDirk Koch, Christian Beckhoff, Jim Torresen. 208-215 [doi]
• The effect of multi-bit based connections on the area efficiency of FPGAs utilizing unidirectional routing resourcesOmesh Mutukuda, Andy Ye, Gul Khan. 216-223 [doi]
• ATB: Area-Time response Balancing algorithm for scheduling real-time hardware tasksXabier Iturbe, Khaled Benkrid, Tughrul Arslan, Imanol Martinez, Mikel Azkarate-askasua. 224-232 [doi]
• Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clustersAnson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk. 233-240 [doi]
• Multi-dimensional packet classification on FPGA: 100 Gbps and beyondYaxuan Qi, Jeffrey Fong, Weirong Jiang, Bo Xu, Jun Li, Viktor K. Prasanna. 241-248 [doi]
• Automatic synthesis of processor arrays with local memories on FPGAsGuiming Wu, Yong Dou, Miao Wang. 249-252 [doi]
• GVE: Godson-T Verification Engine for many-core architecture rapid prototyping and debuggingZhengmeng Lei, Lunkai Zhang, Fenglong Song, Shibin Tang, Dongrui Fan. 253-256 [doi]
• Synthesis of a unified unit for evaluating an application-specific set of elementary functionsLiangwei Ge, Zhenan Tang, Kaiyu Wang, Ming Cao, Wencong Zou, Dong Liu. 257-260 [doi]
• A compression method for inverted index and its FPGA-based decompression solutionJing Yan, Ning-Yi Xu, Zenglin Xia, Rong Luo, Feng-hsiung Hsu. 261-264 [doi]
• FPGA implementation of GZIP compression and decompression for IDC servicesJian Ouyang, Hong Luo, Zilong Wang, Jiazi Tian, Chenghui Liu, Kehua Sheng. 265-268 [doi]
• Application-specific hardware accelerator for implementing recursive sorting algorithmsDmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson. 269-272 [doi]
• Towards an embedded biologically-inspired machine vision processorVinay Sriram, David Cox, Kuen Hung Tsoi, Wayne Luk. 273-278 [doi]
• Wireless sensors networks emulator implemented on a FPGANadim Nasreddine, Jean-Louis Boizard, Christophe Escriba, Jean-Yves Fourniols. 279-282 [doi]
• A novel FPGA-based SVM classifierMarkos Papadonikolakis, Christos-Savvas Bouganis. 283-286 [doi]
• High-throughput IP-lookup supporting dynamic routing tables using FPGAHoang Le, Viktor K. Prasanna. 287-290 [doi]
• A novel design flow for tamper-resistant self-healing properties of FPGA devices without configuration readback capabilityAndré Seffrin, Sunil Malipatlolla, Sorin A. Huss. 291-294 [doi]
• A novel HDL coding style to reduce power consumption for reconfigurable devicesThomas Marconi, Dimitris Theodoropoulos, Koen Bertels, Georgi Gaydadjiev. 295-299 [doi]
• Wire congestion aware synthesis for a dynamically reconfigurable processorTakao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano. 300-303 [doi]
• A FPGA implementation of the two-dimensional Digital Huygens ModelTan Yiyu, Yukinori Sato, Eiko Sugawara, Yasushi Inoguchi, Makoto Otani, Yukio Iwaya, Hiroshi Matsuoka, Takao Tsuchiya. 304-307 [doi]
• Reconfigurable Number Theoretic Transform architectures for cryptographic applicationsGavin Xiaoxu Yao, Ray C. C. Cheung, Çetin Kaya Koç, Kim-Fung Man. 308-311 [doi]
• An FPGA chip identification generator using configurable ring oscillatorHaile Yu, Philip Heng Wai Leong, Qiang Xu. 312-315 [doi]
• FPGA implementation of an interior point solver for linear model predictive controlJuan Luis Jerez, George A. Constantinides, Eric C. Kerrigan. 316-319 [doi]
• General switch box modeling and optimization for FPGA routing architecturesKejie Ma, Lingli Wang, Xuegong Zhou, Sheldon X.-D. Tan, Jiarong Tong. 320-323 [doi]
• Efficient hardware task reuse and interrupt handling mechanisms for FPGA-based partially reconfigurable systemsYi Lu 0004, Koen Bertels, Georgi Gaydadjiev. 324-327 [doi]
• A debugging method for repairing post-silicon bugs of high performance processors in the fieldsBijan Alizadeh, Masahiro Fujita. 328-331 [doi]
• Integration of PSoC technology with educational roboticsJingchuan Wang, Weidong Chen. 332-336 [doi]
• A graphical programming and design environment for FPGA-based hardwareGuoqiang Wang, Trung N. Tran, Hugo A. Andrade. 337-340 [doi]
• Using partial reconfiguration and high-level models to accelerate FPGA design validationYousef Iskander, Stephen D. Craven, Athira Chandrasekharan, Sureshwar Rajagopalan, Guruprasad Subbarayan, Tannous Frangieh, Cameron Patterson. 341-344 [doi]
• FPGA-based video processing for a vision prosthesisBenjamin Kwek, Freddie Sunarso, Melissa Teoh, Arrian van Zal, Philip Preston, Oliver Diessel. 345-348 [doi]
• Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration MappingKazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano. 349-352 [doi]
• Rapid prototyping tools for FPGA designs: RapidSmithChristopher Lavin, Marc Padilla, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings. 353-356 [doi]
• VMODEX: A visualization tool for multi-objective Design Space ExplorationToktam Taghavi, Andy D. Pimentel. 357-360 [doi]
• Advanced partial run-time reconfiguration on Spartan-6 FPGAsDirk Koch, Christian Beckhoff, Jim Tørrison. 361-364 [doi]
• Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGAAmit Kumar Singh, Akash Kumar, Thambipillai Srikanthan, Yajun Ha. 365-368 [doi]
• Design space exploration for sparse matrix-matrix multiplication on FPGAsColin Yu Lin, Zheng Zhang, Ngai Wong, Hayden Kwok-Hay So. 369-372 [doi]
• Accelerating FPGA design space exploration using circuit similarity-based placementXiaoyu Shi, Dahua Zeng, Yu Hu, Guohui Lin, Osmar R. Zaïane. 373-376 [doi]
• Structured ASIC: Methodology and comparisonSam M. H. Ho, Steve C. L. Yuen, Hiu Ching Poon, Thomas C. P. Chau, Yanqing Ai, Philip Heng Wai Leong, Oliver C. S. Choy, Kong-Pang Pun. 377-380 [doi]
• OpenPipes: Making distributed hardware systems easierGlen Gibb, Nick McKeown. 381-384 [doi]
• Design space exploration of instruction schedulers for out-of-order soft processorsKaveh Aasaraai, Andreas Moshovos. 385-388 [doi]
• An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guaranteeZhiyao Joseph Yang, Akash Kumar, Yajun Ha. 389-392 [doi]
• A VLIW softcore processor with dynamically adjustable issue-slotsFakhar Anjam, Muhammad Nadeem, Stephan Wong. 393-398 [doi]
• An FPGA implementation of full-search variable block size motion estimationShuichi Asano, Zheng Zhi Shun, Tsutomu Maruyama. 399-402 [doi]
• A multiported register file with register renaming for configurable softcore VLIW processorsFakhar Anjam, Stephan Wong, Faisal Nadeem. 403-408 [doi]
• A configurable framework for investigating workload executionEric Matthews, Lesley Shannon, Alexandra Fedorova. 409-412 [doi]
• Performance estimation framework for FPGA-based processorsYan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan. 413-416 [doi]
• Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variationsMichitarou Yabuuchi, Kazutoshi Kobayashi. 417-420 [doi]
• Efficient implementation of greyscale morphological filtersDonald G. Bailey. 421-424 [doi]
• A many processing element framework for the Discrete Fourier TransformAndrew van der Byl, Michael Inggs, Richardt H. Wilkinson. 425-428 [doi]
• Acceleration of control flow on CGRA using advanced predicated executionKyuseung Han, Jong Kyung Paek, Kiyoung Choi. 429-432 [doi]
• Efficient implementation of CIOQ switches with sequential iterative matching algorithmsXiaojun Yang, Christoforos Kachris, Manolis Katevenis. 433-436 [doi]
• On identifying and optimizing instruction sequences for dynamic compilationJoão Bispo, João M. P. Cardoso. 437-440 [doi]
• A datapath classification method for FPGA-based scientific application accelerator systemsYui Ogawa, Tomonori Ooya, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri. 441-444 [doi]
• Efficient custom instructions generation for system-level designHuynh Phung Huynh, Yun Liang, Tulika Mitra. 445-448 [doi]
• Histogram-based probability density function estimation on FPGAsSuhaib A. Fahmy. 449-453 [doi]
• A parallel FPGA design of the Smith-Waterman tracebackZubair Nawaz, Muhammad Nadeem, Hans van Someren, Koen Bertels. 454-459 [doi]
• Routing optimizations for component-based system design and partial run-time reconfiguration on FPGAsDirk Koch, Jim Tørresen. 460-464 [doi]
• Solving Sudokus through an incidence matrix on an FPGAMichael Dittrich, Thomas B. Preußer, Rainer G. Spallek. 465-469 [doi]
• GE3: A single FPGA client-server architecture for Golomb Ruler derivationPavlos Malakonakis, Euripides Sotiriades, Apostolos Dollas. 470-473 [doi]
• An FPGA-based scalable platform for high-speed malware collection in large IP networksSascha Mühlbach, Andreas Koch. 474-478 [doi]
• FPGA based soft-core SIMD processing: A MIMO-OFDM Fixed-Complexity Sphere Decoder case studyXuezheng Chu, John McAllister. 479-484 [doi]
• A deeply pipelined and parallel architecture for denoising medical imagesFrank Hannig, Moritz Schmid, Jürgen Teich, Heinz Hornegger. 485-490 [doi]
• SEU tolerant SRAM for FPGA applicationsSudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita. 491-494 [doi]
• Convex models for accelerating applications on FPGA-based clustersQiang Liu, Tim Todman, Kuen Hung Tsoi, Wayne Luk. 495-498 [doi]
• A 64-context MEMS optically reconfigurable gate arrayYuichiro Yamaji, Minoru Watanabe. 499-502 [doi]
• Minimalistic architecture for reconfigurable audio BeamformingDimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev. 503-506 [doi]
• FPGA implementation of a strong Reversi playerJavier Olivito, Carlos González, Javier Resano. 507-510 [doi]
• Othello Solver based on a soft-core MIMD processor arrayTakayuki Mabuchi, Takahiro Watanabe, Retsu Moriwaki, Yuji Aoyama, Amarjargal Gundjalam, Yuichiro Yamaji, Hironari Nakada, Minoru Watanabe. 511-514 [doi]
• CarlOthello : An FPGA-Based Monte Carlo Othello playerMiltiadis Smerdis, Pavlos Malakonakis, Apostolos Dollas. 515-518 [doi]