Mohamed Ismail, Daniel Lo, G. Edward Suh. Improving worst-case cache performance through selective bypassing and register-indexed cache. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015. pages 123, ACM, 2015. [doi]
@inproceedings{IsmailLS15,
title = {Improving worst-case cache performance through selective bypassing and register-indexed cache},
author = {Mohamed Ismail and Daniel Lo and G. Edward Suh},
year = {2015},
doi = {10.1145/2744769.2744855},
url = {http://doi.acm.org/10.1145/2744769.2744855},
researchr = {https://researchr.org/publication/IsmailLS15},
cites = {0},
citedby = {0},
pages = {123},
booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015},
publisher = {ACM},
isbn = {978-1-4503-3520-1},
}