Table of Contents

• An Analysis of Accelerator Coupling in Heterogeneous ArchitecturesEmilio G. Cota, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni. [doi]
• A Lightweight Early Arbitration Method for Low-Latency Asynchronous 2D-Mesh NoC'sWeiWei Jiang, Kshitij Bhardwaj, Geoffray Lacourba, Steven M. Nowick. [doi]
• Power-Performance Modelling of Mobile Gaming Workloads on Heterogeneous MPSoCsAnuj Pathania, Alexandru Eugen Irimiea, Alok Prakash, Tulika Mitra. [doi]
• A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systemsMoomen Chaari, Wolfgang Ecker, Cristiano Novello, Bogdan-Andrei Tabacaru, Thomas Kruse. 1 [doi]
• Evaluation of functional mock-up interface for vehicle power network modelingKenji Nishimiya, Toru Saito, Satoshi Shimada. 2 [doi]
• System simulation from operational dataArmin Wasicek, Edward A. Lee, Hokeun Kim, Lev Greenberg, Akihito Iwai, Ilge Akkaya. 3 [doi]
• New game, new goal posts: a recent history of timing closureAndrew B. Kahng. 4 [doi]
• Walking a thin line: performance and quality grading vs. yield overcutCarl Bowen. 5 [doi]
• Energy efficient MapReduce with VFI-enabled multicore platformsKarthi Duraisamy, Ryan Gary Kim, Wonje Choi, Guangshuo Liu, Partha Pratim Pande, Radu Marculescu, Diana Marculescu. 6 [doi]
• Complementary communication path for energy efficient on-chip optical interconnectsHui Li, Sébastien Le Beux, Yvain Thonnart, Ian O'Connor. 7 [doi]
• On-chip interconnection network for accelerator-rich architecturesJason Cong, Michael Gill, Yuchen Hao, Glenn Reinman, Bo Yuan. 8 [doi]
• Bandwidth-efficient on-chip interconnect designs for GPGPUsHyunjun Jang, Jinchun Kim, Paul Gratz, Ki Hwan Yum, Eun Jung Kim 0001. 9 [doi]
• DimNoC: a dim silicon approach towards power-efficient on-chip networkJia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie 0001. 10 [doi]
• Domain-wall memory buffer for low-energy NoCsDonald Kline Jr., Haifeng Xu, Rami G. Melhem, Alex K. Jones. 11 [doi]
• An EDA framework for large scale hybrid neuromorphic computing systemsWei Wen, Chi-Ruo Wu, Xiaofang Hu, Beiye Liu, Tsung-Yi Ho, Xin Li, Yiran Chen. 12 [doi]
• Merging the interface: power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing systemBoxun Li, Lixue Xia, Peng Gu, Yu Wang, Huazhong Yang. 13 [doi]
• A spiking neuromorphic design with resistive crossbarChenchen Liu, Bonan Yan, Chaofei Yang, Linghao Song, Zheng Li, Beiye Liu, Yiran Chen, Hai Li, Qing Wu, Hao Jiang. 14 [doi]
• Vortex: variation-aware training for memristor X-barBeiye Liu, Hai Li, Yiran Chen, Xin Li, Qing Wu, Tingwen Huang. 15 [doi]
• Jump test for metallic CNTs in CNFET-based SRAMFeng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang. 16 [doi]
• A reconfigurable analog substrate for highly efficient maximum flow computationGai Liu, Zhiru Zhang. 17 [doi]
• Robust design of E/E architecture component platformsSebastian Graf, Sebastian Reinhart, Michael Glaß, Jürgen Teich, Daniel Platte. 18 [doi]
• RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memoryYing Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li. 19 [doi]
• Area and performance co-optimization for domain wall memory in application-specific embedded systemsShouzhen Gu, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Yiran Chen, Jingtong Hu. 20 [doi]
• Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAMRujia Wang, Lei Jiang, Youtao Zhang, Linzhang Wang, Jun Yang. 21 [doi]
• Interleaved multi-bank scratchpad memories: a probabilistic description of access conflictsAndreas Tretter, Pratyush Kumar, Lothar Thiele. 22 [doi]
• PRES: pseudo-random encoding scheme to increase the bit flip reduction in the memorySeyed Mohammad Seyedzadeh, Rakan Maddah, Alex K. Jones, Rami G. Melhem. 23 [doi]
• Guidelines to design parity protected write-back L1 data cacheYohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava. 24 [doi]
• Construction of reconfigurable clock trees for MCMM designsRickard Ewetz, Shankarshana Janarthanan, Cheng-Kok Koh. 25 [doi]
• A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reductionKwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee. 26 [doi]
• Routing-architecture-aware analytical placement for heterogeneous FPGAsSheng-Yen Chen, Yao-Wen Chang. 27 [doi]
• PARR: pin access planning and regular routing for self-aligned double patterningXiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan. 28 [doi]
• Local search algorithms for timing-driven placement under arbitrary delay modelsAdrian Bock, Stephan Held, Nicolas Kämmerling, Ulrike Schorr. 29 [doi]
• 3DIC benefit estimation and implementation guidance from 2DIC implementationWei-Ting Jonas Chan, Siddhartha Nath, Andrew B. Kahng, Yang Du, Kambiz Samadi. 30 [doi]
• DERA: yet another differential fault attack on cryptographic devices based on error rate analysisYannan Liu, Jie Zhang, Lingxiao Wei, Feng Yuan, Qiang Xu. 31 [doi]
• Vibration-based secure side channel for medical devicesYounghyun Kim, Woo Suk Lee, Vijay Raghunathan, Niraj K. Jha, Anand Raghunathan. 32 [doi]
• Information leakage chaff: feeding red herrings to side channel attackersGiovanni Agosta, Alessandro Barenghi, Gerardo Pelosi, Michele Scandale. 33 [doi]
• TyTAN: tiny trust anchor for tiny devicesFranz Ferdinand Brasser, Brahim El Mahjoub, Ahmad-Reza Sadeghi, Christian Wachsmann, Patrick Koeberl. 34 [doi]
• Memory heat map: anomaly detection in real-time embedded systems using memory behaviorMan-Ki Yoon, Lui Sha, Sibin Mohan, Jaesik Choi. 35 [doi]
• Compacting privacy-preserving k-nearest neighbor search using logic synthesisEbrahim M. Songhori, Siam U. Hussain, Ahmad-Reza Sadeghi, Farinaz Koushanfar. 36 [doi]
• Battery lifetime-aware automotive climate control for electric vehiclesKorosh Vatanparvar, Mohammad Abdullah Al Faruque. 37 [doi]
• Security analysis of automotive architectures using probabilistic model checkingPhilipp Mundhenk, Sebastian Steinhorst, Martin Lukasiewycz, Suhaib A. Fahmy, Samarjit Chakraborty. 38 [doi]
• Security aware network controllers for next generation automotive embedded systemsShanker Shreejith, Suhaib A. Fahmy. 39 [doi]
• Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verificationJaime Espinosa, Carles Hernández, Jaume Abella, David de Andrés, Juan Carlos Ruiz. 40 [doi]
• Improving formal timing analysis of switched ethernet by exploiting FIFO schedulingDaniel Thiele, Philip Axer, Rolf Ernst. 41 [doi]
• Parallel execution of AUTOSAR legacy applications on multicore ECUs with timed implicit communicationSebastian Kehr, Eduardo Quiñones, Bert Böddeker, Günter Schäfer. 42 [doi]
• Nautilus: fast automated IP design space search using guided genetic algorithmsMichael K. Papamichael, Peter Milder, James C. Hoe. 43 [doi]
• Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architecturesSascha Roloff, David Schafhauser, Frank Hannig, Jürgen Teich. 44 [doi]
• Acceleration of control flows on reconfigurable architecture with a composite methodJunbin Wang, Leibo Liu, Jianfeng Zhu, Shouyi Yin, Shaojun Wei. 45 [doi]
• GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designsMunish Jassi, Daniel Müller-Gritschneder, Ulf Schlichtmann. 46 [doi]
• ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computingYing Wang, Yinhe Han, Lei Zhang 0008, Huawei Li, Xiaowei Li. 47 [doi]
• Trends in functional verification: a 2014 industry studyHarry D. Foster. 48 [doi]
• Verifying SystemC using stateful symbolic simulationVladimir Herdt, Hoang M. Le, Rolf Drechsler. 49 [doi]
• In-circuit temporal monitors for runtime verification of reconfigurable designsTim Todman, Stephan Stilkerich, Wayne Luk. 50 [doi]
• Sequential equivalence checking of clock-gated circuitsYu-Yun Dai, Kei-Yong Khoo, Robert K. Brayton. 51 [doi]
• Verification of gate-level arithmetic circuits by function extractionMaciej J. Ciesielski, Cunxi Yu, Walter Brown, Duo Liu, André Rossi. 52 [doi]
• Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principlesKeith A. Campbell, David Lin, Subhasish Mitra, Deming Chen. 53 [doi]
• Security and privacy challenges in industrial internet of thingsAhmad-Reza Sadeghi, Christian Wachsmann, Michael Waidner. 54 [doi]
• Blocking unsafe behaviors in control systems through static and dynamic policy enforcementStephen McLaughlin. 55 [doi]
• Timing-aware control software design for automotive systemsDirk Ziegenbein, Arne Hamann. 56 [doi]
• Compositional modeling and analysis of automotive feature product linesShankara Narayanan Krishna, Ganesh Khandu Narwane, S. Ramesh, Ashutosh Trivedi. 57 [doi]
• The challenge of interoperability: model-based integration for automotive control softwareHuafeng Yu, Prachi Joshi, Jean-Pierre Talpin, Sandeep K. Shukla, Shin'ichi Shiraishi. 58 [doi]
• Introduction to stochastic computing and its challengesJohn P. Hayes. 59 [doi]
• An introduction into fault-tolerant quantum computingAlexandru Paler, Simon J. Devitt. 60 [doi]
• Design automation challenges for scalable quantum architecturesIlia Polian, Austin G. Fowler. 61 [doi]
• A control-theoretic approach for energy efficient CPU-GPU subsystem in mobile platformsDavid Kadjo, Raid Ayoub, Michael Kishinevsky, Paul V. Gratz. 62 [doi]
• Opportunistic turbo execution in NTC: exploiting the paradigm shift in performance bottlenecksHu Chen, Dieudonne Manzi, Sanghamitra Roy, Koushik Chakraborty. 63 [doi]
• Domain wall memory based digital signal processors for area and energy-efficiencyJinil Chung, Kenneth Ramclam, Jongsun Park, Swaroop Ghosh. 64 [doi]
• DaTuM: dynamic tone mapping technique for OLED display power saving based on video classificationXiang Chen, Yiran Chen, Chun Jason Xue. 65 [doi]
• RENO: a high-efficient reconfigurable neuromorphic computing accelerator designXiaoxiao Liu, Mengjie Mao, Beiye Liu, Hai Li, Yiran Chen, Boxun Li, Yu Wang, Hao Jiang, Mark Barnell, Qing Wu, Jianhua Yang. 66 [doi]
• Scalable-effort classifiers for energy-efficient machine learningSwagath Venkataramani, Anand Raghunathan, Jie Liu, Mohammed Shoaib. 67 [doi]
• Evaluation of BEOL design rule impacts using an optimal ILP-based detailed routerKwangsoo Han, Andrew B. Kahng, Hyein Lee. 68 [doi]
• Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithographyYixiao Ding, Chris C. N. Chu, Wai-Kei Mak. 69 [doi]
• Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/viasYasmine Badr, Andres Torres, Puneet Gupta. 70 [doi]
• High performance dummy fill insertion with coupling and uniformity constraintsYibo Lin, Bei Yu, David Z. Pan. 71 [doi]
• An efficient shift invariant rasterization algorithm for all-angle mask patterns in ILTYixiao Ding, Chris C. N. Chu, Xin Zhou. 72 [doi]
• Effective model-based mask fracturing for mask cost reductionAbde Ali Kagalwalla, Puneet Gupta. 73 [doi]
• HAFIX: hardware-assisted flow integrity extensionLucas Davi, Matthias Hanreich, Debayan Paul, Ahmad-Reza Sadeghi, Patrick Koeberl, Dean Sullivan, Orlando Arias, Yier Jin. 74 [doi]
• Performance analysis of a memristive crossbar PUF designGarrett S. Rose, Chauncey A. Meade. 75 [doi]
• Adaptive characterization and emulation of delay-based physical unclonable functions using statistical modelsTeng Xu, Dongfang Li, Miodrag Potkonjak. 76 [doi]
• Self-correcting STTRAM under magnetic field attacksJae-Won Jang, Jongsun Park, Swaroop Ghosh, Swarup Bhunia. 77 [doi]
• On using control signals for word-level identification in a gate-level netlistEdward Tashjian, Azadeh Davoodi. 78 [doi]
• Efficient dynamic information flow tracking on a processor with core debug interfaceJinYong Lee, Ingoo Heo, Yongje Lee, Yunheung Paek. 79 [doi]
• What don't we know about CPS architectures?Marilyn Wolf, Eric Feron. 80 [doi]
• Design tool chain for cyber-physical systems: lessons learnedJanos Sztipanovits, Ted Bapty, Sandeep Neema, Xenofon D. Koutsoukos, Ethan K. Jackson. 81 [doi]
• Models, abstractions, and architectures: the missing links in cyber-physical systemsBharathan Balaji, Mohammad Abdullah Al Faruque, Nikil D. Dutt, Rajesh K. Gupta, Yuvraj Agarwal. 82 [doi]
• VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applicationsMengjie Mao, Jingtong Hu, Yiran Chen, Hai Li. 83 [doi]
• Revisiting accelerator-rich CMPs: challenges and solutionsNasibeh Teimouri, Hamed Tabkhi, Gunar Schirner. 84 [doi]
• SuperNet: multimode interconnect architecture for manycore chipsHaseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran. 85 [doi]
• A low latency generic accuracy configurable adderMuhammad Shafique, Waqas Ahmad, Rehan Hafiz, Jörg Henkel. 86 [doi]
• A 127 fps in full hd accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extractionGuangli Jiang, Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei. 87 [doi]
• Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memoryRujia Wang, Lei Jiang, Youtao Zhang, Linzhang Wang, Jun Yang. 88 [doi]
• Understanding soft errors in uncore componentsHyungmin Cho, Chen-Yong Cher, Thomas Shepherd, Subhasish Mitra. 89 [doi]
• Interconnect reliability modeling and analysis for multi-branch interconnect treesHai-Bao Chen, Sheldon X.-D. Tan, Valeriy Sukharev, Xin Huang, Taeyoung Kim. 90 [doi]
• Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAMYarui Peng, Bon Woong Ku, Youn-Sik Park, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Sung Kyu Lim. 91 [doi]
• Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applicationsShreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim. 92 [doi]
• Novel power grid reduction method based on L1 regularizationYe Wang, Meng Li, Xinyang Yi, Zhao Song, Michael Orshansky, Constantine Caramanis. 93 [doi]
• A statistical methodology for noise sensor placement and full-chip voltage map generationXiaochen Liu, Shupeng Sun, Pingqiang Zhou, Xin Li, Haifeng Qian. 94 [doi]
• Cloning your mind: security challenges in cognitive system designs and their solutionsBeiye Liu, Chunpeng Wu, Hai Li, Yiran Chen, Qing Wu, Mark Barnell, Qinru Qiu. 95 [doi]
• Design and verification for transportation system securityBowen Zheng, Wenchao Li, Peng Deng, Léonard Gérard, Qi Zhu, Natarajan Shankar. 96 [doi]
• Impact assessment of net metering on smart home cyberattack detectionYang Liu, Shiyan Hu, Jie Wu, Yiyu Shi, Yier Jin, Yu Hu, Xiaowei Li. 97 [doi]
• Ensuring functional safety compliance for ISO 26262Adam D. Sherer, John Rose, Riccardo Oddone. 98 [doi]
• Automating design-space exploration: optimal deployment of automotive SW-components in an ISO26262 contextBernhard Schätz, Sebastian Voss, Sergey Zverlov. 99 [doi]
• Energy-efficient non-volatile TCAM search engine design using priority-decision in memory technology for DPIHsiang-Jen Tsai, Keng-Hao Yang, Yin-Chi Peng, Chien-Chen Lin, Ya-Han Tsao, Meng-Fan Chang, Tien-Fu Chen. 100 [doi]
• EnAAM: energy-efficient anti-aging for on-chip video memoriesMuhammad Shafique, Muhammad Usman Karim Khan, Adnan Orcun Tüfek, Jörg Henkel. 101 [doi]
• Mitigating the impact of faults in unreliable memories for error-resilient applicationsShrikanth Ganapathy, Georgios Karakonstantis, Adam Teman, Andreas Burg. 102 [doi]
• A STT-RAM-based low-power hybrid register file for GPGPUsGushu Li, Xiaoming Chen, Guangyu Sun, Henry Hoffmann, Yongpan Liu, Yu Wang, Huazhong Yang. 103 [doi]
• Joint precision optimization and high level synthesis for approximate computingChaofan Li, Wei Luo, Sachin S. Sapatnekar, Jiang Hu. 104 [doi]
• b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point unitsG. Tziantzioulis, A. M. Gok, S. M. Faisal, Nikolaos Hardavellas, Seda Ogrenci Memik, Srinivasan Parthasarathy. 105 [doi]
• ΣVP: host-GPU multiplexing for efficient simulation of multiple embedded GPUs on virtual platformsYoungHoon Jung, Luca P. Carloni. 106 [doi]
• HARS: a heterogeneity-aware runtime system for self-adaptive multithreaded applicationsJaeyoung Yun, Jinsu Park, Woongki Baek. 107 [doi]
• Accelerating real-time embedded scene labeling with convolutional networksLukas Cavigelli, Michele Magno, Luca Benini. 108 [doi]
• SmartBalance: a sensing-driven linux load balancer for energy efficiency of heterogeneous MPSoCsSantanu Sarma, T. Muck, Luis Angel D. Bathen, Nikil D. Dutt, Alexandru Nicolau. 109 [doi]
• Optimizing stream program performance on CGRA-based systemsHongsik Lee, Dong Nguyen, Jongeun Lee. 110 [doi]
• Detecting hardware trojans using backside optical imaging of embedded watermarksBoyou Zhou, Ronen Adato, Mahmoud Zangeneh, Tianyu Yang, Aydan Uyar, Bennett B. Goldberg, M. Selim Ünlü, Ajay Joshi. 111 [doi]
• Detecting malicious modifications of data in third-party intellectual property coresJeyavijayan Rajendran, Vivekananda Vedula, Ramesh Karri. 112 [doi]
• A practical circuit fingerprinting method utilizing observability don't care conditionsCarson Dunbar, Gang Qu. 113 [doi]
• Investigation of obfuscation-based anti-reverse engineering for printed circuit boardsZ. Guo, Mark Tehranipoor, Domenic Forte, J. Di. 114 [doi]
• Leveraging on-chip voltage regulators as a countermeasure against side-channel attacksWeize Yu, Orhun Aras Uzun, Selçuk Köse. 115 [doi]
• Highly efficient entropy extraction for true random number generators on FPGAsVladimir Rozic, Bohan Yang, Wim Dehaene, Ingrid Verbauwhede. 116 [doi]
• Design & verification of automotive SoC firmwareVeit B. Kleeberger, Stefan Rutkowski, Ruth Coppens. 117 [doi]
• Model-based testing of automotive software: some challenges and solutionsAlexandre Petrenko, Omer Nguena-Timo, S. Ramesh. 118 [doi]
• New trends in dark siliconJörg Henkel, Heba Khdr, Santiago Pagani, Muhammad Shafique. 119 [doi]
• Approximate computing and the quest for computing efficiencySwagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan. 120 [doi]
• Core vs. uncore: the heart of darknessHsiang-Yun Cheng, Jia Zhan, Jishen Zhao, Yuan Xie 0001, Jack Sampson, Mary Jane Irwin. 121 [doi]
• A generic representation of CCSL time constraints for UML/MARTE modelsJudith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler. 122 [doi]
• Improving worst-case cache performance through selective bypassing and register-indexed cacheMohamed Ismail, Daniel Lo, G. Edward Suh. 123 [doi]
• PACO: fast average-performance estimation for time-randomized cachesSuzana Milutinovic, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla. 124 [doi]
• Increasing confidence on measurement-based contention bounds for real-time round-robin busesGabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla. 125 [doi]
• Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migrationDaming Zhang, Yongpan Liu, Xiao Sheng, Jinyang Li, Tongda Wu, Chun Jason Xue, Huazhong Yang. 126 [doi]
• Efficient design space exploration of embedded platformsMartin Lukasiewycz, Florian Sagstetter, Sebastian Steinhorst. 127 [doi]
• One-pass logic synthesis for graphene-based Pass-XNOR logic circuitsValerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino. 128 [doi]
• OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditionsSubhendu Roy, Derong Liu, Junhyung Um, David Z. Pan. 129 [doi]
• Scalable sequence-constrained retention register minimization in power gating designTing Wei Chiang, Kai-Hui Chang, Yen-Ting Liu, Jie-Hong R. Jiang. 130 [doi]
• Equivalence among stochastic logic circuits and its applicationTe-Hsuan Chen, John P. Hayes. 131 [doi]
• Randomness meets feedback: stochastic implementation of logistic map dynamical systemZhiheng Wang, Naman Saraf, Kia Bazargan, Arnd Scheel. 132 [doi]
• A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-ICRunjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron, Mircea R. Stan. 133 [doi]
• Optimal control of PEVs for energy cost minimization and frequency regulation in the smart grid accounting for battery state-of-health degradationTiansong Cui, Yanzhi Wang, Shuang Chen, Qi Zhu, Shahin Nazarian, Massoud Pedram. 134 [doi]
• Evaluating battery aging on mobile devicesJaeseong Lee, Yohan Chon, Hojung Cha. 135 [doi]
• Design for low test pattern countsHaluk Konuk, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Deepak Solanki, Jerzy Tyszer, Justyna Zawada. 136 [doi]
• Generation of close-to-functional broadside tests with equal primary input vectorsIrith Pomeranz. 137 [doi]
• Nanowire-aware routing considering high cut mask complexityYu-Hsuan Su, Yao-Wen Chang. 138 [doi]
• Optimizing data placement for reducing shift operations on domain wall memoriesXianzhang Chen, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Penglin Dai, Weiwen Jiang. 139 [doi]
• A SPICE model of flexible transition metal dichalcogenide field-effect transistorsYing-Yu Chen, Zelei Sun, Deming Chen. 140 [doi]
• Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mappingTsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann. 141 [doi]
• PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochipsHailong Yao, Tsung-Yi Ho, Yici Cai. 142 [doi]
• Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM designJoydeep Rakshit, Runlai Wan, Kai-Tak Lam, Jing Guo, Kartik Mohanram. 143 [doi]
• SoC security architecture: current practices and emerging needsEric Peeters. 144 [doi]
• Pre-silicon security verification and validation: a formal perspectiveXiaolong Guo, Raj Gautam Dutta, Yier Jin, Farimah Farahmandi, Prabhat Mishra. 145 [doi]
• Correctness and security at odds: post-silicon validation of modern SoC designsSandip Ray, Jin Yang, Abhishek Basak, Swarup Bhunia. 146 [doi]
• Joint automatic control of the powertrain and auxiliary systems to enhance the electromobility in hybrid electric vehiclesYanzhi Wang, Xue Lin, Massoud Pedram, Naehyuck Chang. 147 [doi]
• Formal methods for semi-autonomous drivingSanjit A. Seshia, Dorsa Sadigh, S. Shankar Sastry. 148 [doi]
• Integrated power management in IoT devices under wide dynamic ranges of operationSamantak Gangopadhyay, Saad Bin Nasir, Arijit Raychowdhury. 149 [doi]
• Ambient energy harvesting nonvolatile processors: from circuit to systemYongpan Liu, Zewei Li, Hehe Li, Yiqun Wang, Xueqing Li, Kaisheng Ma, Shuangchen Li, Meng-Fan Chang, Sampson John, Yuan Xie 0001, Jiwu Shu, Huazhong Yang. 150 [doi]
• ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scalingMohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Divya Pathak, Ioannis Savidis, Houman Homayoun. 151 [doi]
• Task scheduling strategies to mitigate hardware variability in embedded shared memory clustersAbbas Rahimi, Daniele Cesarini, Andrea Marongiu, Rajesh K. Gupta, Luca Benini. 152 [doi]
• Including variability of physical models into the design automation of cyber-physical systemsHamid Mirzaei Buini, Steffen Peter, Tony Givargis. 153 [doi]
• PASS: priority assignment of real-time tasks with dynamic suspending behavior under fixed-priority schedulingWen-Hung Huang, Jian-Jia Chen, Husheng Zhou, Cong Liu. 154 [doi]
• Resource usage templates and signatures for COTS multicore processorsGabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla. 155 [doi]
• Dynamically adaptive scrubbing mechanism for improved reliability in reconfigurable embedded systemsRui Santos, Shyamsundar Venkataraman, Akash Kumar. 156 [doi]
• Area-efficient pipelining for FPGA-targeted high-level synthesisRitchie Zhao, Mingxing Tan, Steve Dai, Zhiru Zhang. 157 [doi]
• CMOST: a system-level FPGA compilation frameworkPeng Zhang, Muhuan Huang, Bingjun Xiao, Hui Huang 0001, Jason Cong. 158 [doi]
• Avoiding transitional effects in dynamic circuit specialisation on FPGAsKarel Heyse, Dirk Stroobandt. 159 [doi]
• Efficient memory partitioning for parallel data access in multidimensional arraysChenyue Meng, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei. 160 [doi]
• High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapathsKeith A. Campbell, Pranay Vissa, David Z. Pan, Deming Chen. 161 [doi]
• Physically aware high level synthesis design flowMasato Tatsuoka, Ryosuke Watanabe, Tatsushi Otsuka, Takashi Hasegawa, Qiang Zhu, Ryosuke Okamura, Xingri Li, Tsuyoshi Takabatake. 162 [doi]
• An algorithmic framework for efficient large-scale circuit simulation using exponential integratorsHao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, Chung-Kuan Cheng. 163 [doi]
• Variation aware cross-talk aggressor alignment by mixed integer linear programmingVladimir Zolotov, Peter Feldmann. 164 [doi]
• TA-FTA: transition-aware functional timing analysis with a four-valued encodingJasper C. C. Chang, Ryan H.-M. Huang, Louis Y.-Z. Lin, Charles H.-P. Wen. 165 [doi]
• An efficient algorithm for statistical timing yield optimizationS. Ramprasath, V. Vasudevan. 166 [doi]
• Criticality-dependency-aware timing characterization and analysisYu-Ming Yang, King Ho Tam, Iris Hui-Ru Jiang. 167 [doi]
• A timing graph based approach to mode mergingSubramanyam Sripada, Murthy Palla. 168 [doi]
• Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuitsQicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li. 169 [doi]
• mTunes: efficient post-silicon tuning of mixed-signal/RF integrated circuits based on Markov decision processManzil Zaheer, Fa Wang, Chenjie Gu, Xin Li. 170 [doi]
• Towards enhancing analog circuits sizing using SMT-based techniquesOns Lahiouel, Mohamed H. Zaki, Sofiène Tahar. 171 [doi]
• Verifying inevitability of phase-locking in a charge pump phase lock loop using sum of squares programmingHafiz ul Asad, Kevin D. Jones. 172 [doi]
• Adaptive compressed sensing architecture in wireless brain-computer interfaceAosen Wang, Zhanpeng Jin, Chen Song, Wenyao Xu. 173 [doi]
• A low power unsupervised spike sorting accelerator insensitive to clustering initialization in sub-optimal feature spaceZhewei Jiang, Qi Wang, Mingoo Seok. 174 [doi]
• The SIMON and SPECK lightweight block ciphersRay Beaulieu, Douglas Shors, Jason Smith, Stefan Treatman-Clark, Bryan Weeks, Louis Wingers. 175 [doi]
• EM attack sensor: concept, circuit, and design-automation methodologyNoriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Naofumi Homma, Yu-ichi Hayashi, Takafumi Aoki. 176 [doi]
• Design and integration challenges of building security hardware IPMegan Wachs, Daniel Ip. 177 [doi]
• Achieving power and reliability sign-off for automotive semiconductor designsAjay Kashyap, Soenke Grimpen, Shyam Sundaramoorthy. 178 [doi]
• Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chipsHeba Khdr, Santiago Pagani, Muhammad Shafique, Jörg Henkel. 179 [doi]
• Hayat: harnessing dark silicon and variability for aging deceleration and balancingDennis Gnad, Muhammad Shafique, Florian Kriebel, Semeen Rehman, Duo Sun, Jörg Henkel. 180 [doi]
• Network footprint reduction through data access and computation placement in NoC-based manycoresJun Liu, Jagadish Kotra, Wei Ding, Mahmut T. Kandemir. 181 [doi]
• Designing time partitions for real-time hypervisor with sufficient temporal independenceMatthias Beckert, Rolf Ernst. 182 [doi]
• Compiler directed automatic stack trimming for efficient non-volatile processorsQing'an Li, Mengying Zhao, Jingtong Hu, Yongpan Liu, Yanxiang He, Chun Jason Xue. 183 [doi]
• Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processorMimi Xie, Mengying Zhao, Chen Pan, Jingtong Hu, Yongpan Liu, Chun Jason Xue. 184 [doi]
• Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systemsLengfei Han, Zhuo Feng. 185 [doi]
• Parallel circuit simulation using the direct method on a heterogeneous cloudAhmed E. Helal, Amr M. Bayoumi, Yasser Y. Hanafy. 186 [doi]
• An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor formVinita Vasudevan, M. Ramakrishna. 187 [doi]
• Design tools for oscillator-based computing systemsTianshi Wang, Jaijeet Roychowdhury. 188 [doi]
• Layout-dependent-effects-aware analytical analog placementHung-Chih Ou, Kai-Han Tseng, Jhao-Yan Liu, I.-Peng Wu, Yao-Wen Chang. 189 [doi]
• Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithographyHung-Chih Ou, Kai-Han Tseng, Yao-Wen Chang. 190 [doi]
• To collect or not to collect: just-in-time garbage collection for high-performance SSDs with long lifetimesSangwook Shane Hahn, Jihong Kim, Sungjin Lee. 191 [doi]
• Achieving SLC performance with MLC flash memoryYu-Ming Chang, Yuan-Hao Chang, Tei-Wei Kuo, Yung-Chun Li, Hsiang-Pang Li. 192 [doi]
• Virtual flash chips: rethinking the layer design of flash devices to improve data recoverabilityMing-Chang Yang, Yuan-Hao Chang, Tei-Wei Kuo. 193 [doi]
• FlexLevel: a novel NAND flash storage system design for LDPC latency reductionJie Guo, Wujie Wen, Jingtong Hu, Danghui Wang, Hai Li, Yiran Chen. 194 [doi]
• Approximate storage for energy efficient spintronic memoriesAshish Ranjan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan. 195 [doi]
• A synthesis methodology for application-specific logic-in-memory designsH. Ekin Sumbul, Kaushik Vaidyanathan, Qiuling Zhu, Franz Franchetti, Larry Pileggi. 196 [doi]
• Pushing multiple patterning in sub-10nm: are we ready?David Z. Pan, Lars Liebmann, Bei Yu, Xiaoqing Xu, Yibo Lin. 197 [doi]
• EUV and e-beam manufacturability: challenges and solutionsYao-Wen Chang, Ru-Gun Liu, Shao-Yun Fang. 198 [doi]
• Layout optimization and template pattern verification for directed self-assembly (DSA)Zigang Xiao, Daifeng Guo, Martin D. F. Wong, He Yi, Maryann C. Tung, H.-S. Philip Wong. 199 [doi]
• Virtual to the (near) end: using virtual platforms for continuous integrationJakob Engblom. 200 [doi]