A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS

Kenichi Iwata, Seiji Mochizuki, Motoki Kimura, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Koji Hosogi, Hiroaki Nakata, Masakazu Ehama, Toru Kengaku, Takuichiro Nakazawa, Hiromi Watanabe. A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS. J. Solid-State Circuits, 44(4):1184-1191, 2009. [doi]

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.