Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata. Pipelined Architecture for Additive Range Reduction. VLSI Signal Processing, 53(1-2):103-112, 2008. [doi]
@article{JaimeVHZ08,
title = {Pipelined Architecture for Additive Range Reduction},
author = {Francisco J. Jaime and Julio Villalba and Javier Hormigo and Emilio L. Zapata},
year = {2008},
doi = {10.1007/s11265-008-0166-x},
url = {http://dx.doi.org/10.1007/s11265-008-0166-x},
tags = {architecture},
researchr = {https://researchr.org/publication/JaimeVHZ08},
cites = {0},
citedby = {0},
journal = {VLSI Signal Processing},
volume = {53},
number = {1-2},
pages = {103-112},
}